X40010S8I-A Intersil, X40010S8I-A Datasheet - Page 7

• Manufacturer Part Number: X40010S8I-A
• Description: IC VOLTAGE MONITOR DUAL 8-SOIC
• Manufacturer: Intersil
• Type: Multi-Voltage Supervisorr

Specifications of X40010S8I-A

• Number Of Voltages Monitored: 2
• Output: Push-Pull, Totem Pole
• Reset: Active High
• Reset Timeout: Adjustable/Selectable
• Voltage - Threshold: 2.9V, 4.6V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PUP1, PUP0: Power Up Bits (Nonvolatile)
The Power Up bits, PUP1 and PUP0, determine the
t
shown in the following table.
WD1, WD0: Watchdog Timer Bits (Nonvolatile)
The bits WD1 and WD0 control the period of the
Watchdog Timer. The options are shown below.
Writing to the Control Registers
Changing any of the nonvolatile bits of the control and
trickle registers requires the following steps:
– Write a 02H to the Control Register to set the Write
– Write a 06H to the Control Register to set the
– Write a one byte value to the Control Register that
PURST
PUP1
WD1
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation pre-
ceded by a start and ended with a stop).
Register Write Enable Latch (RWEL) and the WEL
bit. This is also a volatile cycle. The zeros in the data
byte are required. (Operation proceeded by a start
and ended with a stop).
has all the control bits set to the desired state. The
Control register can be represented as qxys 001r in
binary, where xy are the WD bits, s isthe BP bit and
qr are the power up bits. This operation proceeded
by a start and ended with a stop bit. Since this is a
nonvolatile write cycle it will take up to 10ms to
complete. The RWEL bit is reset by this cycle and
the sequence must be repeated to change the non-
volatile bits again. If bit 2 is set to ‘1’ in this third step
(qxys 011r) then the RWEL bit is set, but the WD1,
WD0, PUP1, PUP0, and BP bits remain unchanged.
Writing a second byte to the control register is not
allowed. Doing so aborts the write operation and
returns a NACK.
0
0
1
1
0
0
1
1
time delay. The nominal power up times are
PUP0
WD0
0
1
0
1
0
1
0
1
Power on Reset Delay (
Watchdog Time Out Period
disabled (factory setting)
200ms (factory setting)
7
200 milliseconds
25 milliseconds
1.4 seconds
400ms
800ms
50ms
X40010, X40011, X40014, X40015
t
PURST
)
– A read operation occurring between any of the
– The RWEL bit cannot be reset without writing to the
To illustrate, a sequence of writes to the device con-
sisting of [02H, 06H, 02H] will reset all of the nonvola-
tile bits in the Control Register to 0. A sequence of
[02H, 06H, 06H] will leave the nonvolatile bits
unchanged and the RWEL bit remains set.
FAULT DETECTION REGISTER
The Fault Detection Register (FDR) provides the user
the status of what causes the system reset active. The
Manual Reset Fail, Watchdog Timer Fail and three
Low Voltage Fail bits are volatile.
The FDR is accessed with a special preamble in the
slave byte (1011) and is located at address 0FFh. It
can only be modified by performing a byte write
operation directly to the address of the register and
only one data byte is allowed for each register write
operation.
There is no need to set the WEL or RWEL in the
control register to access this fault detection register.
LV1F
previous operations will not interrupt the register
write operation.
nonvolatile control bits in the control register, power
cycling the device or attempting a write to a write
protected block.
7
LV2F
6
5
0
WDF
4
3
0
2
0
March 28, 2005
1
0
FN8111.0
0
0