X40010V8-AT1 Intersil, X40010V8-AT1 Datasheet
X40010V8-AT1
Specifications of X40010V8-AT1
Related parts for X40010V8-AT1
X40010V8-AT1 Summary of contents
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... All other trademarks mentioned are the property of their respective owners. FN8111.0 activates the power on reset CC and WDO RESET X40010/14 Power on, RESET Reset X40011/15 V2FAIL Intersil (and design registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved ...
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... Three common low voltage combinations are available, however, Intersil’s unique circuits allows the threshold for either voltage monitor to be repro- grammed to meet special needs or to fine-tune the threshold for applications requiring higher precision ...
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PIN DESCRIPTION (Continued) Pin SOIC TSSOP Name 6 8 SCL Serial Clock. The Serial Clock controls the serial bus timing for data input and output WDO WDO Output. WDO is an active LOW, open drain output which goes ...
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Figure 2. V Set/Reset Conditions TRIPX TRIPX WDO 0 SCL SDA A0h WATCHDOG TIMER The Watchdog Timer circuit monitors the microprocessor activity by monitoring the SDA and SCL pins. The micro- processor must toggle the ...
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Resetting the V Voltage TRIPx To reset a V voltage, apply the programming volt- TRIPx age (Vp) to the WDO pin before a START condition is set up on SDA. Next, issue on the SDA pin the Slave Address A0h ...
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Figure 5. V Set/Reset Sequence ( TRIPX New V applied = X Old V applied + | Error | X Error < MDE WEL: Write Enable Latch (Volatile) The WEL bit controls the access to the memory ...
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PUP1, PUP0: Power Up Bits (Nonvolatile) The Power Up bits, PUP1 and PUP0, determine the time delay. The nominal power up times are t PURST shown in the following table. PUP1 PUP0 Power on Reset Delay ( 0 0 50ms ...
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Figure 6. Valid Data Changes on the SDA Bus SCL SDA At power-up, the Fault Detection Register is defaulted to all “0”. The system needs to initialize this register to all “1” before the actual monitoring take place. In the ...
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Figure 7. Valid Start and Stop Conditions SCL SDA Serial Acknowledge Acknowledge is a software convention used to indi- cate successful data transfer. The transmitting device, either master or slave, will release the bus after trans- mitting eight bits. During ...
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Read Operation Prior to issuing the Slave Address Byte with the R/W bit set to one, the master must first perform a “dummy” write operation. The master issues the start condition and the Slave Address Byte, receives an acknowledge, then ...
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Figure 10. Acknowledge Polling Sequence Byte Load Completed by Issuing STOP. Enter ACK Polling Issue START Issue Slave Address Byte (Read or Write) NO ACK Returned? YES High Voltage Cycle Complete. Continue Command Sequence? YES Continue Normal Read or Write ...
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SERIAL DEVICE ADDRESSING Memory Address Map CR, Control Register, CR7: CR0 Address: 1FF hex FDR, Fault DetectionRegister, FDR7: FDR0 Address: 0FF hex Slave Address Byte Following a start condition, the master must output a Slave Address Byte. This byte consists ...
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Word Address The word address is either supplied by the master or obtained from an internal counter. The internal counter is undefined on a power up condition. Operational Notes The device powers-up in the following state: – The device is ...
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ABSOLUTE MAXIMUM RATINGS Temperature under bias .................... -65°C to +135°C Storage temperature ......................... -65°C to +150°C Voltage on any pin with respect to V ...................................... -1.0V to +7V SS D.C. output current ............................................... 5mA Lead temperature (soldering, 10 seconds) ........ ...
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D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified) Symbol Parameter Second Supply Monitor I V2MON Current V2 (5) V V2MON Trip Point Voltage Range TRIP2 Notes: (1) The device enters the Active state after any start, and ...
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EQUIVALENT A.C. OUTPUT LOAD CIRCUIT FOR OUT 4.6KΩ 2.06KΩ RESET SDA WDO 30pF 30pF A.C. TEST CONDITIONS Input pulse levels V CC Input rise and fall times 10ns Input and output timing levels V ...
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A.C. CHARACTERISTICS Symbol f SCL Clock Frequency SCL t Pulse width Suppression Time at inputs IN t SCL LOW to SDA Data Out Valid AA t Time the bus free before start of new transmission BUF t Clock LOW Time ...
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Write Cycle Timing SCL th SDA 8 Bit of Last Byte Nonvolatile Write Cycle Timing Symbol (1) t Write Cycle Time WC Note: ( the time from a valid stop condition at the end of a write sequence ...
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RESET/RESET Timings V TRIP1 PURST t R RESET V RVALID RESET LOW VOLTAGE AND WATCHDOG TIMING PARAMETERS Symbol ( RESET/RESET (Power down only) RPD1 TRIP1 ( V2FAIL RPDX TRIP2 Power On ...
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Watchdog Time Out For 2-Wire Interface Start SCL SDA WDO Minimum Sequence to Reset WDT SCL SDA V Set/Reset Conditions TRIPX (V TRIPX t TSU WDO t VPS SCL 0 SDA A0h Start 20 X40010, X40011, X40014, X40015 Start Clockin ...
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Programming Specifications: V TRIP1 TRIP2 Parameter t WDO Program Voltage Setup time VPS t WDO Program Voltage Hold time VPH t V Level Setup time TSU TRIPX t V Level Hold (stable) time THD TRIPX t ...
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PACKAGING INFORMATION Pin 1 Index 0.010 (0.25) 0.020 (0.50) 0° - 8° 0.016 (0.410) 0.037 (0.937) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 22 X40010, X40011, X40014, X40015 8-Lead Plastic, SOIC, Package Code S8 Pin 1 0.014 (0.35) ...
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PACKAGING INFORMATION 0° - 8° See Detail “A” NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 23 X40010, X40011, X40014, X40015 8-Lead Plastic, TSSOP, Package Code V8 .025 (.65) BSC .169 (4.3) .177 (4.5) .114 (2.9) .122 (3.1) .047 ...
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... X40010S8-A X40011S8 X40010S8I-A X40011S8I X40010V8-A X40011V8 X40010V8I-A X40011V8I X40010S8-B X40011S8 X40010S8I-B X40011S8I X40010V8-B X40011V8 X40010V8I-B X40011V8I X40010S8-C X40011S8 X40010S8I-C X40011S8I X40010V8-C X40011V8 X40010V8I-C X40011V8I X40014S8-A X40015S8 X40014S8I-A X40015S8I X40014V8-A X40015V8 X40014V8I-A X40015V8I X40014S8-B X40015S8 X40014S8I-B X40015S8I X40014V8-B X40015V8 X40014V8I-B X40015V8I X40014S8-C ...