X5045V14I-2.7 Intersil, X5045V14I-2.7 Datasheet - Page 12

• Manufacturer Part Number: X5045V14I-2.7
• Description: IC SUPERVISOR CPU 4K EE 14-TSSOP
• Manufacturer: Intersil
• Type: Simple Reset/Power-On Resetr

Specifications of X5045V14I-2.7

• Number Of Voltages Monitored: 1
• Output: Open Drain or Open Collector
• Reset: Active High
• Reset Timeout: 100 ms Minimum
• Voltage - Threshold: 2.62V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Operational Notes
The device powers-up in the following state:
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
• A WREN instruction must be issued to set the Write
• CS must come HIGH at the proper clock count in order to
• Block Protect bits provide additional level of write
• The WP pin LOW blocks nonvolatile write operations.
1. The device is in the low power standby state.
2. A HIGH to LOW transition on CS is required to enter an
3. SO pin is high impedance.
4. The Write Enable Latch is reset.
5. The Flag Bit is reset.
6. Reset Signal is active for t
Enable Latch.
start a nonvolatile write cycle.
protection for the memory array.
active state and receive an instruction.
SCK
SCK
CS
CS
SI
SI
24 25 26 27 28 29 30 31
7
6
0
5
12
Data Byte 2
PURST
1
Instruction
4
2
.
3
3
2
4
8
1
9
FIGURE 9. WRITE MEMORY SEQUENCE
5
th
0
Bit of Address
6
32 33 34 35 36 37 38 39
7
7
6
X5043, X5045
8
7
5
Data Byte 3
6
9
4
8 Bit Address
10
5
3
2
12 13 14 15 16 17 18 19 20 21 22 23
3
1
2
0
1
0
6
7
5
6
Data Byte N
4
5
3
Data Byte 1
4
2
3
1
2
0
1
0
March 16, 2006
FN8126.2