LP38512MRX-ADJ/NOPB National Semiconductor, LP38512MRX-ADJ/NOPB Datasheet - Page 9

• Manufacturer Part Number: LP38512MRX-ADJ/NOPB
• Description: IC REG LDO 1.5A ADJ 8-PSOP
• Manufacturer: National Semiconductor

Specifications of LP38512MRX-ADJ/NOPB

• Regulator Topology: Positive Adjustable
• Voltage - Output: 0.5 ~ 4.5 V
• Voltage - Input: 2.25 ~ 5.5 V
• Number Of Regulators: 1
• Current - Output: 1.5A (Max)
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-PSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Dropout (typical): -
• Current - Limit (min): -
• Other names: LP38512MRX-ADJ

causes the thermal shutdown circuit to respond to servo the
on/off cycling to a lower frequency. Please refer to the POW-
ER DISSIPATION/HEAT-SINKING section for power dissi-
pation calculations.
SETTING THE OUTPUT VOLTAGE
The output voltage is set using the external resistive divider
R1 and R2. The output voltage is given by the formula:
The resistors used for R1 and R2 should be high quality, tight
tolerance, and with matching temperature coefficients. It is
important to remember that, although the value of V
guaranteed, the final value of V
quality resistors for R1 and R2 can easily produce a V
value that is unacceptable.
It is recommended that the values selected for R1 and R2 are
such that the parallel value is less than 1.00 kΩ. This is to
reduce the possibility of any internal parasitic capacitances
on the ADJ pin from creating an undesirable phase shift that
may interfere with device stability.
FEED FORWARD CAPACITOR, C
When using a ceramic capacitor for C
value will be too small to provide any meaningful positive
phase compensation, F
shifts in the gain loop.
A capacitor placed across the gain resistor R1 will provide
additional phase margin to improve load transient response
of the device. This capacitor, C
a zero in the loop response given by the formula:
For optimum load transient response select C
frequency, F
The phase lead provided by C
approaches unity, or V
C
It's important to note that at higher output voltages, where R1
is much larger than R2, the pole and zero are far apart in fre-
quency. At lower output voltages the frequency of the pole
and the zero mover closer together. The phase lead provided
from C
and has no effect when V
FF
also forms a pole with a frequency of:
FF
diminishes quickly as the output voltage is reduced,
( (R1 x R2) / (R1 + R2) )
F
P
F
Z
V
= 1 / (2 x
Z
, falls between 20 kHz and 40 kHz.
F
C
OUT
= 1 / (2 x
Z
FF
= 1 / (2 x
= 1 / (2 x
= V
ADJ
OUT
π
Z
, to offset the internal negative phase
π
x C
OUT
x (1 + (R1/R2))
π
approaches V
x C
π
FF
x C
= V
x R1 x F
FF
OUT
FF
x (R1 || R2) )
FF
, in parallel with R1, will form
OUT
ADJ
diminishes as the DC gain
≤
x ESR)
x R1)
FF
. For this reason, relying
1.00 kΩ
is not. The use of low
Z
OUT
)
ADJ
, the typical ESR
. This is because
FF
so the zero
ADJ
OUT
(1)
(2)
(3)
(4)
(5)
(6)
is
9
on this compensation technique alone is adequate only for
higher output voltages.
Table 1 lists some suggested, best fit, standard ±1% resistor
values for R1 and R2, and a standard ±10% capacitor values
for C
and C
Please refer to Application Note AN-1378 Method For Calcu-
lating Output Voltage Tolerances in Adjustable Regulators for
additional information on how resistor tolerances affect the
calculated V
ENABLE OPERATION
The Enable ON threshold is typically 1.2V, and the OFF
threshold is typically 1.0V. To ensure reliable operation the
Enable pin voltage must rise above the maximum V
threshold and must fall below the minimum V
old. The Enable threshold has typically 200mV of hysteresis
to improve noise immunity.
The Enable pin (EN) has no internal pull-up or pull-down to
establish a default condition and, as a result, this pin must be
terminated either actively or passively.
If the Enable pin is driven from a single ended device (such
as the collector of a discrete transistor) a pull-up resistor to
V
proper operation. A 1 kΩ to 100 kΩ resistor can be used as
the pull-up or pull-down resistor to establish default condition
for the EN pin. The resistor value selected should be appro-
priate to swamp out any leakage in the external single ended
device, as well as any stray capacitance.
If the Enable pin is driven from a source that actively pulls high
and low (such as a CMOS rail to rail comparator output), the
pull-up, or pull-down, resistor is not required.
If the application does not require the Enable function, the pin
should be connected directly to the adjacent V
POWER DISSIPATION/HEAT-SINKING
A heat-sink may be required depending on the maximum
power dissipation (P
(T
the package. Under all possible conditions, the junction tem-
perature (T
ating Ratings. The total power dissipation of the device is
given by:
where I
(specified under Electrical Characteristics).
IN
0.80V
1.00V
1.20V
1.50V
1.80V
2.00V
2.50V
3.00V
3.30V
A(MAX)
V
, or a pull-down resistor to ground, will be required for
OUT
FF
FF
, for a range of V
P
)of the application, and the thermal resistance (θ
GND
D
are available that will give similar results.
= ( (V
J
1.07 kΩ
1.00 kΩ
1.40 kΩ
2.00 kΩ
2.94 kΩ
1.02 kΩ
1.02 kΩ
1.00 kΩ
2.00 kΩ
) must be within the range specified in the Oper-
OUT
is the operating ground current of the device
R
1
IN
value.
−V
OUT
D(MAX)
) x I
1.78 kΩ
1.00 kΩ
1.00 kΩ
1.00 kΩ
1.13 kΩ
OUT
TABLE 1.
340Ω
255Ω
200Ω
357Ω
), maximum ambient temperature
R
OUT
2
values. Other values of R1, R2,
) + ((V
4700 pF
4700 pF
3300 pF
2700 pF
1500 pF
4700 pF
4700 pF
4700 pF
2700 pF
IN
C
) x I
FF
GND
EN(OFF)
IN
)
www.national.com
pin.
31.6 kHz
33.8 kHz
34.4 kHz
29.5 kHz
33.2 kHz
33.2 kHz
33.8 kHz
29.5 kHz
36.1kHz
F
thresh-
Z
EN(ON)
JA
) of
(7)