USB6B1RL STMicroelectronics, USB6B1RL Datasheet - Page 4

IC TRANSIENT OVERVOLT PROT 8SOIC

USB6B1RL

Manufacturer Part Number
USB6B1RL
Description
IC TRANSIENT OVERVOLT PROT 8SOIC
Manufacturer
STMicroelectronics
Datasheet

Specifications of USB6B1RL

Voltage - Clamping
6V
Technology
Mixed Technology
Power (watts)
500W
Number Of Circuits
2
Applications
USB
Package / Case
8-SOIC (3.9mm Width)
Polarity
Bidirectional
Operating Voltage
5.25 V
Breakdown Voltage
6 V
Termination Style
SMD/SMT
Peak Surge Current
40 A
Peak Pulse Power Dissipation
500 W
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Dimensions
3.9 mm W x 4.9 mm L x 1.75 mm H
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Voltage - Working
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
497-3281-2

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Technical information
2
2.1
Note:
2.2
Important: An imortant precaution to take is to put the protection device closer to the disturbance
4/9
Technical information
Surge protection
The USB6B1 is optimized to perform surge protection based on the rail to rail topology.
The clamping voltage V
with: V
V
The estimations do not take into account phenomena due to parasitic inductances.
How to ensure good ESD protection
While the USB6B1 provides a high immunity to ESD surge, an efficient protection depends
on the layout of the board. In the same way, with the rail to rail topology, the track from the
V
possible to avoid overvoltages due to parasitic phenomena (see
It’s often harder to connect the power supply near to the USB6B1 unlike the ground thanks
to the ground plane that allows a short connection. To ensure the same efficiency for
positive surges when the connections can’t be short enough, we recommend to putting a
100 nF c apacitor close to the USB6B1 between V
overvoltage disturbances (see
protection by providing a constant voltage during the surge.
Figure 6.
described above.
source (generally the connection).
Figure 4.
F
CC
= forward drop voltage, V
V
V
pin to the power supply and from the GND pin to GND voltage must be as short as
Vcc+Vf
Lw di
CL
CL
F
dt
SURGE
+ = V
=V
ESD
- = - V
shows the improvement of the ESD protection according to the recommendations
VI/O
tr=1ns
Vcl+
t
POSITIVE
+ r
SURGE
Surge behavior
Lw di
CC
d
dt
F
I/O
.Ip
GND
for negative surges
+ V
Vf
Vcl+ = Vcc+Vf+Lw
Vcl- =
t
F
for positive surges
Lw di
CL
Lw
-Vf- Lw
dt
-Lw
can be estimated as follow:
-Vf
dt
di
dt
di
t
dt
di
= forward drop threshold voltage
tr=1ns
+Vcc
Vcl-
Figure
surge >0
surge <0
NEGATIVE
SURGE
5.) The addition of this capacitor offers better
t
Figure 5.
CC
SURGE
ESD
and ground to prevvent these kinds of
VI/O
Vcl+
POSITIVE
SURGE
ESD behavior: optimized
layout and addition of a
100 nF capacitor
I/O
REF1=GND
Figure
C=100nF
Vcl+ = Vcc+Vf
Vcl- =
t
Lw
-Vf
4.)
Vcl-
NEGATIVE
surge >0
surge <0
SURGE
REF2=+Vcc
t
USB6B1