CM1213-06MR ON Semiconductor, CM1213-06MR Datasheet - Page 10

• Manufacturer Part Number: CM1213-06MR
• Description: TVS ARRAY ESD PROT LOW 6CH 8MSOP
• Manufacturer: ON Semiconductor

Specifications of CM1213-06MR

• Voltage - Reverse Standoff (typ): 3.3V
• Voltage - Breakdown: 6V
• Power (watts): 400mW
• Polarization: 6 Channel Array - Bidirectional
• Mounting Type: Surface Mount
• Package / Case: 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Application Information
Design Considerations
In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to
minimize parasitic series inductances on the Supply/Ground rails as well as the signal trace segment between
the signal input (typically a connector) and the ESD protection device. Refer to Application of Positive ESD
Pulse between Input Channel and Ground, which illustrates an example of a positive ESD pulse striking an input
channel. The parasitic series inductance back to the power supply is represented by L
on the line being protected is:
where I
An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact
discharge per the IEC61000-4-2 standard results in a current pulse that rises from zero to 30 Amps in 1ns. Here
d(I
will lead to a 300V increment in V
Similarly for negative ESD pulses, parasitic series inductance from the V
drastically increased negative voltage on the line being protected.
The CM1213 has an integrated Zener diode between V
inductance L
possible V
recommended that a 0.22µF ceramic chip capacitor be connected between V
As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of
expected electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to
the V
planes and between the signal input and the ESD device to minimize stray series inductance.
Additional Information
See also California Micro Devices Application Note AP209, “Design Considerations for ESD Protection”, in the
Applications section at www.calmicro.com.
ESD
V
CL
)/dt can be approximated by ∆I
P
pin of the Protection Array as possible, with minimum PCB trace lengths to the power supply, ground
ESD
+ L
2
is the ESD current pulse, and V
=
CL
x d(I
, especially when V
2
Figure 3. Application of Positive ESD Pulse between Input Channel and Ground
on V
ESD
Fwd
)
/
dt
CL
by clamping V
voltage
P
CL
is biased at a voltage significantly below the Zener breakdown voltage, it is
!
drop
ESD
P
/∆t, or 30/(1x10
at the breakdown voltage of the Zener diode. However, for the lowest
Rev. 3 | Page 10 of 17 | www.onsemi.com
SUPPLY
of
is the positive supply voltage.
D
1
-9
). So just 10nH of series inductance (L
P
+
and V
V
SUPPLY
N
. This greatly reduces the effect of supply rail
+
N
P
pin to the ground rail will lead to
and the ground plane.
L
1
x
1
and L
d(I
ESD
1
2
. The voltage V
and L
CM1213
)
2
combined)
/
dt
CL