MC908JL3EMPE Freescale Semiconductor, MC908JL3EMPE Datasheet - Page 27

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MC908JL3EMPE

Manufacturer Part Number
MC908JL3EMPE
Description
IC MCU 4K FLASH W/OSC 28-PDIP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908JL3EMPE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Peripherals
LED, LVD, POR, PWM
Number Of I /o
23
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
28-DIP (0.600", 15.24mm)
Processor Series
HC08JL
Core
HC08
Data Bus Width
8 bit
Data Ram Size
128 B
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
23
Number Of Timers
2
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
Development Tools By Supplier
FSICEBASE, DEMO908JL16E, M68CBL05CE
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
 Details
2.4 Random-Access Memory (RAM)
Addresses $0080 through $00FF are RAM locations. The location of the stack RAM is programmable.
The 16-bit stack pointer allows the stack to be anywhere in the 64-Kbyte memory space.
Within page zero are 128 bytes of RAM. Because the location of the stack RAM is programmable, all page
zero RAM locations can be used for I/O control and user data or code. When the stack pointer is moved
from its reset location at $00FF, direct addressing mode instructions can access efficiently all page zero
RAM locations. Page zero RAM, therefore, provides ideal locations for frequently accessed global
variables.
Before processing an interrupt, the CPU uses five bytes of the stack to save the contents of the CPU
registers.
Freescale Semiconductor
For correct operation, the stack pointer must point only to RAM locations.
Vector Priority
Highest
Lowest
For M6805 compatibility, the H register is not stacked.
INT Flag
MC68HC908JL3E Family Data Sheet, Rev. 4
IF15
IF14
IF13
IF6
IF5
IF4
IF3
IF2
IF1
Table 2-1. Vector Addresses
Address
$FFDD
$FFD0
$FFDE
$FFDF
$FFFB
$FFFC
$FFFD
$FFFE
$FFE0
$FFE1
$FFF2
$FFF3
$FFF4
$FFF5
$FFF6
$FFF7
$FFFA
$FFFF
NOTE
NOTE
Not Used
ADC Conversion Complete Vector (High)
ADC Conversion Complete Vector (Low)
Keyboard Vector (High)
Keyboard Vector (Low)
Not Used
TIM Overflow Vector (High)
TIM Overflow Vector (Low)
TIM Channel 1 Vector (High)
TIM Channel 1 Vector (Low)
TIM Channel 0 Vector (High)
TIM Channel 0 Vector (Low)
Not Used
IRQ Vector (High)
IRQ Vector (Low)
SWI Vector (High)
SWI Vector (Low)
Reset Vector (High)
Reset Vector (Low)
Vector
Random-Access Memory (RAM)
27

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