MC9S08RD32DWER Freescale Semiconductor, MC9S08RD32DWER Datasheet - Page 24

• Manufacturer Part Number: MC9S08RD32DWER
• Description: IC MCU 8BIT 32K FLASH 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08RD32DWER

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SOIC (0.300", 7.50mm Width)
• Processor Series: S08RD
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SCI1, SPI1
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 39
• Number Of Timers: 2
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08RG60E
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Pins and Connections
2.3.4
The background/mode select function is shared with an output-only port function on the PTD0/BKDG/MS
pin. While in reset, the pin functions as a mode select pin. Immediately after reset rises, the pin functions
as the background pin and can be used for background debug communication. While functioning as a
background/mode select pin, this pin has an internal pullup device enabled. To use as an output-only port,
BKGDPE in SOPT must be cleared.
If nothing is connected to this pin, the MCU will enter normal operating mode at the rising edge of reset.
If a debug system is connected to the 6-pin standard background debug header, it can hold BKGD/MS low
during the rising edge of reset, which forces the MCU to active background mode.
The BKGD pin is used primarily for background debug controller (BDC) communications using a custom
protocol that uses 16 clock cycles of the target MCU’s BDC clock per bit time. The target MCU’s BDC
clock could be as fast as the bus clock rate, so there should never be any significant capacitance connected
to the BKGD/MS pin that could interfere with background serial communications.
Although the BKGD pin is a pseudo open-drain pin, the background debug communication protocol
provides brief, actively driven, high speedup pulses to ensure fast rise times. Small capacitances from
cables and the absolute value of the internal pullup device play almost no role in determining rise and fall
times on the BKGD pin.
2.3.5
The IRO pin is the output of the CMT. See the
detailed description of this pin function.
2.3.6
The remaining pins are shared among general-purpose I/O and on-chip peripheral functions such as timers
and serial I/O systems. (Not all pins are available in all packages. See
all 37 of these pins are configured as high-impedance general-purpose inputs with internal pullup devices
disabled.
For information about controlling these pins as general-purpose I/O pins, see the
Input/Output." For information about how and when on-chip peripheral systems use these pins, refer to the
appropriate chapter from
24
Background/Mode Select (PTD0/BKGD/MS)
IRO Pin Description
General-Purpose I/O and Peripheral Ports
To avoid extra current drain from floating input pins, the reset initialization
routine in the application program should either enable on-chip pullup
devices or change the direction of unused pins to outputs so the pins do not
float.
Table
2-1.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Carrier Modulator Timer (CMT) Module Chapter
NOTE
Table
2-2.) Immediately after reset,
Chapter 6, “Parallel
Freescale Semiconductor
for a