XR20M1172IG28-F Exar Corporation, XR20M1172IG28-F Datasheet - Page 14

• Manufacturer Part Number: XR20M1172IG28-F
• Description: IC UART FIFO I2C/SPI 64B 28TSSOP
• Manufacturer: Exar Corporation

Specifications of XR20M1172IG28-F

• Number Of Channels: 2, DUART
• Package / Case: 28-TSSOP (0.173", 4.40mm Width)
• Features: *
• Fifo's: 64 Byte
• Protocol: RS485
• Voltage - Supply: 1.62 V ~ 3.63 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 16 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.62 V
• Supply Current: 250 uA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• No. Of Channels: 2
• Uart Features: Tx/Rx FIFO Counters
• Supply Voltage Range: 1.62V To 3.63V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: TSSOP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1298-5

XR20M1172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO
When using 4X sampling mode, the bit time will have a jitter of ± 1/8 whenever DLD is non-zero, odd and not a
multiple of 4. When using a non-standard data rate crystal or external clock, the divisor value can be
calculated with the following equation(s):
The closest divisor that is obtainable in the M1172 can be calculated using the following formula:
In the formulas above, please note that:
TRUNC (N) = Integer Part of N. For example, TRUNC (5.6) = 5.
ROUND (N) = N rounded towards the closest integer. For example, ROUND (7.3) = 7 and ROUND (9.9) = 10.
A >> B indicates right shifting the value ’A’ by ’B’ number of bits. For example, 0x78A3 >> 8 = 0x0078.
F
IGURE
ROUND( (Required Divisor - TRUNC(Required Divisor) )*16)/16 + TRUNC(Required Divisor), where
Required Divisor (decimal)=(XTAL1 clock frequency / prescaler) /(serial data rate x 16), with 16X mode, DLD[5:4]=’00’
Required Divisor (decimal)= (XTAL1 clock frequency / prescaler / (serial data rate x 8), with 8X mode, DLD[5:4] = ’01’
Required Divisor (decimal)= (XTAL1 clock frequency / prescaler / (serial data rate x 4), with 4X mode, DLD[5:4] = ’10’
12. B
AUD
XTAL2
XTAL1
R
ATE
DLD = ROUND( (Required Divisor-TRUNC(Required Divisor) )*16)
G
ENERATOR
Crystal
Buffer
Osc/
DLL = TRUNC(Required Divisor) & 0xFF
DLM = TRUNC(Required Divisor) >> 8
Divide by 4
Divide by 1
Prescaler
Prescaler
14
MCR Bit-7=0
MCR Bit-7=1
(default)
DLL, DLM and DLD
Fractional Baud
Rate Generator
Registers
Logic
16X or 8X or 4X
and Receiver
to Transmitter
Rate Clock
Sampling
REV. 1.0.1