ST16C654CQ100-F Exar Corporation, ST16C654CQ100-F Datasheet - Page 11

• Manufacturer Part Number: ST16C654CQ100-F
• Description: IC UART FIFO 64B QUAD 100QFP
• Manufacturer: Exar Corporation
• Type: IrDAr

Specifications of ST16C654CQ100-F

• Number Of Channels: 4, QUART
• Package / Case: 100-LQFP
• Features: *
• Fifo's: 64 Byte
• Protocol: RS232
• Voltage - Supply: 2.97 V ~ 5.5 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 1.5 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.97 V
• Supply Current: 6 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V or 5 V
• No. Of Channels: 4
• Uart Features: Infrared (IrDA) Encoder/Decoder
• Supply Voltage Range: 2.97V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: QFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1270

xr
REV. 5.0.2
Each UART channel in the 654 has a set of enhanced registers for control, monitoring and data loading and
unloading. The configuration register set is compatible to those already available in the standard single
16C550. These registers function as data holding registers (THR/RHR), interrupt status and control registers
(ISR/IER), a FIFO control register (FCR), receive line status and control registers (LSR/LCR), modem status
and control registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/DLM), and a user
accessible scratchpad register (SPR).
Beyond the general 16C550 features and capabilities, the 654 offers enhanced feature registers (EFR, Xon/
Xoff 1, Xon/Xoff 2, FSTAT) that provide automatic RTS and CTS hardware flow control and automatic Xon/Xoff
software flow control. All the register functions are discussed in full detail later in
INTERNAL REGISTERS” on page
The interrupt outputs change according to the operating mode and enhanced features setup.
summarize the operating behavior for the transmitter and receiver. Also see
The device does not support direct memory access. The DMA Mode (a legacy term) in this document does not
mean “direct memory access” but refers to data block transfer operation. The DMA mode affects the state of
the RXRDY# A-D and TXRDY# A-D output pins. The transmit and receive FIFO trigger levels provide
additional flexibility to the user for block mode operation. The LSR bits 5-6 provide an indication when the
transmitter is empty or has an empty location(s) for more data. The user can optionally operate the transmit
and receive FIFO in the DMA mode (FCR bit-3=1). When the transmit and receive FIFOs are enabled and the
DMA mode is disabled (FCR bit-3 = 0), the 654 is placed in single-character mode for data transmit or receive
operation. When DMA mode is enabled (FCR bit-3 = 1), the user takes advantage of block mode operation by
loading or unloading the FIFO in a block sequence determined by the programmed trigger level. The following
table show their behavior. Also see
2.4
2.5
2.6
INT Pin
INT Pin
Channels A-D Internal Registers
INT Ouputs for Channels A-D
DMA Mode
0 = no data
1 = 1 byte
0 = a byte in THR
1 = THR empty
(FIFO D
(FIFO D
FCR B
FCR B
T
ABLE
T
ABLE
IT
ISABLED
IT
ISABLED
-0 = 0
-0 = 0
3: INT P
4: INT P
)
)
22.
INS
Figure 20
IN
0 = FIFO above trigger level
0 = FIFO below trigger level
1 = FIFO above trigger level
O
O
1 = FIFO below trigger level or FIFO
empty
PERATION FOR
PERATION FOR
(DMA Mode Disabled)
through 25.
(DMA Mode Disabled)
FCR Bit-3 = 0
FCR Bit-3 = 0
11
T
RANSMITTER FOR
R
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
ECEIVER FOR
FCR B
FCR B
IT
IT
-0 = 1 (FIFO E
-0 = 1 (FIFO E
C
HANNELS
C
0 = FIFO above trigger level
0 = FIFO below trigger level
1 = FIFO above trigger level
HANNELS
Figure 20
1 = FIFO below trigger level or FIFO
empty
NABLED
NABLED
(DMA Mode Enabled)
(DMA Mode Enabled)
A-D
A-D
FCR Bit-3 = 1
through 25.
FCR Bit-3 = 1
)
)
“Section 3.0, UART
ST16C654/654D
Table 3 and 4