ST16C654CQ100-F Exar Corporation, ST16C654CQ100-F Datasheet - Page 30

• Manufacturer Part Number: ST16C654CQ100-F
• Description: IC UART FIFO 64B QUAD 100QFP
• Manufacturer: Exar Corporation
• Type: IrDAr

Specifications of ST16C654CQ100-F

• Number Of Channels: 4, QUART
• Package / Case: 100-LQFP
• Features: *
• Fifo's: 64 Byte
• Protocol: RS232
• Voltage - Supply: 2.97 V ~ 5.5 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 1.5 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.97 V
• Supply Current: 6 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V or 5 V
• No. Of Channels: 4
• Uart Features: Infrared (IrDA) Encoder/Decoder
• Supply Voltage Range: 2.97V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: QFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1270

ST16C654/654D
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
LCR[5]: TX and RX Parity Select
If the parity bit is enabled, LCR BIT-5 selects the forced parity format.
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LCR[6]: Transmit Break Enable
When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a
“space’, logic 0, state). This condition remains, until disabled by setting LCR bit-6 to a logic 0.
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LCR[7]: Baud Rate Divisors Enable
Baud rate generator divisor (DLL/DLM) enable.
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The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs.
MCR[0]: DTR# Output
The DTR# pin is a modem control output. If the modem interface is not used, this output may be used as a
general purpose output.
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MCR[1]: RTS# Output
The RTS# pin is a modem control output and may be used for automatic hardware flow control by enabled by
EFR bit-6. If the modem interface is not used, this output may be used as a general purpose output.
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MCR[2]: Reserved
OP1# is not available as an output pin on the 654. But it is available for use during Internal Loopback Mode. In
the Loopback Mode, this bit is used to write the state of the modem RI# interface signal.
4.7
LCR BIT-5 = logic 0, parity is not forced (default).
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive
data.
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive
data.
Logic 0 = No TX break condition. (default)
Logic 1 = Forces the transmitter output (TX) to a “space”, logic 0, for alerting the remote receiver of a line
break condition.
Logic 0 = Data registers are selected. (default)
Logic 1 = Divisor latch registers are selected.
Logic 0 = Force DTR# output to a logic 1 (default).
Logic 1 = Force DTR# output to a logic 0.
Logic 0 = Force RTS# output to a logic 1 (default).
Logic 1 = Force RTS# output to a logic 0.
Modem Control Register (MCR) or General Purpose Outputs Control - Read/Write
LCR B
X
0
0
1
1
IT
-5 LCR B
T
ABLE
X
0
1
0
1
IT
-4 LCR B
13: P
ARITY SELECTION
30
0
1
1
1
1
IT
-3
Force parity to mark,
P
Forced parity to
ARITY SELECTION
Even parity
Odd parity
space, “0”
No parity
“1”
xr
REV. 5.0.2