XR17V358IB176-F Exar Corporation, XR17V358IB176-F Datasheet - Page 29
![IC UART PCIE OCTAL 176FPBGA](/photos/28/69/286931/176-lfbga_sml.jpg)
XR17V358IB176-F
Manufacturer Part Number
XR17V358IB176-F
Description
IC UART PCIE OCTAL 176FPBGA
Manufacturer
Exar Corporation
Datasheet
1.XR17V358IB176-F.pdf
(68 pages)
Specifications of XR17V358IB176-F
Number Of Channels
1, UART
Package / Case
176-LFBGA
Features
*
Fifo's
256 Byte
Protocol
RS485
Voltage - Supply
1.2V, 3.3V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
Mounting Type
Surface Mount
Data Rate
25 Mbps
Supply Current
120 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3.3 V
No. Of Channels
8
Uart Features
Tx/Rx FIFO Counters
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
-40°C To +85°C
Digital Ic Case Style
BGA
No. Of Pins
176
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
1016-1296 - EVAL BOARD FOR XR17V358-E81016-1295 - EVAL BOARD FOR XR17V358-E41016-1293 - EVAL BOARD FOR XR17V358
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
1016-1294
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XR17V358IB176-F
Manufacturer:
EXAR
Quantity:
1 700
Company:
Part Number:
XR17V358IB176-F
Manufacturer:
Exar Corporation
Quantity:
10 000
Part Number:
XR17V358IB176-F
Manufacturer:
EXAR/艾科嘉
Quantity:
20 000
REV. 1.0.2
MPIOINT [15:0] (default 0x00)
The MPIOINT register enables the multipurpose input pin interrupt. If an MPIO pin is selected by MPIOSEL as
an input, then it can be selected to generate an interrupt. MPIOINT bit[0] enables input pin MPIO0 for interrupt,
and bit [7] enables input pin 7. No interrupt is enable if the pin is selected to be an output. The interrupt is edge
sensing and determined by MPIOINV and MPIOLVL registers. The MPIO interrupt clears after a read to
register MPIOLVL. The combination of MPIOLVL and MPIOINV determines the interrupt being active LOW or
active HIGH. Logic 0 (default) disables the pin’s interrupt and logic 1 enables it.
MPIOLVL [15:0] (default 0x00)
The MPIOLVL register controls the output pins and provides the input level status for the input pins. The status
of the input pin(s) is read on this register and output pins are controlled on this register. A logic 0 (default) sets
the output to LOW and a logic 1 sets the output pin to HIGH. The MPIO interrupt will clear upon reading this
register.
MPIO3T [15:0] (default 0x00)
The MPIO outputs can be tri-stated by the MPIO3T register. A logic 0 (default) sets the output to active level
per register MPIOBIT settling, a logic 1 sets the output pin to tri-state.
MPIOINV [15:0] (default 0x00)
The MPIO inputs can be inverted by the MPIOINV register. A logic 0 (default) does not invert the input pin logic.
A logic 1 inverts the input logic level.
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
MPIO7
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
MPIO7
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
MPIO7
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
MPIO7
Multipurpose Input Signal Inversion Enable
Multipurpose Input/Output Interrupt Enable
MPIO6
MPIO6
MPIO6
MPIO6
Multipurpose Output Level Control
Multipurpose Output 3-state Enable
MPIO5 MPIO4 MPIO3 MPIO2 MPIO1 MPIO0
MPIO5 MPIO4 MPIO3 MPIO2 MPIO1 MPIO0
MPIO5 MPIO4 MPIO3 MPIO2 MPIO1 MPIO0
MPIO5 MPIO4 MPIO3 MPIO2 MPIO1 MPIO0
MPIOLVL Register
MPIOINV Register
MPIOINT Register
MPIO3T Register
29
HIGH PERFORMANCE OCTAL PCI EXPRESS UART
XR17V358