71M6521FE-IGT/F Maxim Integrated Products, 71M6521FE-IGT/F Datasheet - Page 23

• Manufacturer Part Number: 71M6521FE-IGT/F
• Description: IC ENERGY METER 32K FLASH 64LQFP
• Manufacturer: Maxim Integrated Products

Specifications of 71M6521FE-IGT/F

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

71M6521DE/DH/FE Data Sheet
FLSHCRL
WDI
INTBITS
Instruction Set
All instructions of the generic 8051 microcontroller are supported. A complete list of the instruction set and of the
associated op-codes is contained in the 71M6521 Software User’s Guide (SUG).
UART
The 71M6521DE/DH/FE includes a UART (UART0) that can be programmed to communicate with a variety of AMR
modules. A second UART (UART1) is connected to the optical port, as described in the optical port description.
The UARTs are dedicated 2-wire serial interfaces, which can communicate with an external host processor at up to
38,400 bits/s (with MPU clock = 1.2288MHz). The operation of each pin is as follows:
RX: Serial input data are applied at this pin. Conforming to RS-232 standard, the bytes are input LSB first.
TX: This pin is used to output the serial data. The bytes are output LSB first.
The 71M6521DE/DH/FE has several UART-related registers for the control and buffering of serial data. All UART
transfers are programmable for parity enable, parity, 2 stop bits/1 stop bit and XON/XOFF options for variable
communication baud rates from 300 to 38400 bps. Table 13 shows how the baud rates are calculated. Table 14
shows the selectable UART operation modes.
Rev 2
INT0…INT6
0xB2
0xE8
0xF8
Table 12: Special Function Registers
R/W
R/W
R/W
R/W
W
W
R
R
DPTR.
This bit is automatically reset after each byte written to flash. Writes
to this bit are inhibited when interrupts are enabled.
Bit 0 (FLSH_PWE): Program Write Enable:
(default).
Bit 1 (FLSH_MEEN): Mass Erase Enable:
Must be re-written for each new Mass Erase cycle.
Bit 6 (SECURE):
Enables security provisions that prevent external reading of flash
memory and CE program RAM. This bit is reset on chip reset and
may only be set. Attempts to write zero are ignored.
Bit 7 (PREBOOT):
Indicates that the preboot sequence is active.
The multi-purpose register WDI contains the following bits:
Bit 0 (IE_XFER): XFER Interrupt Flag:
This flag monitors the XFER_BUSY interrupt. It is set by hardware
and must be cleared by the interrupt handler
Bit 1 (IE_RTC): RTC Interrupt Flag:
This flag monitors the RTC_1SEC interrupt. It is set by hardware and
must be cleared by the interrupt handler
Bit 7 (WD_RST): WD Timer Reset:
Read: Reads the PLL_FALL interrupt flag
Write 0: Clears the PLL_FALL interrupt flag
Write 1: Resets the watch dog timer
Interrupt inputs. The MPU may read these bits to see the input to
external interrupts INT0, INT1, up to INT6. These bits do not have
any memory and are primarily intended for debug use
0 – MOVX commands refer to XRAM Space, normal operation
1 – MOVX @DPTR,A moves A to Program Space (Flash) @
0 – Mass Erase disabled (default).
1 – Mass Erase enabled.
Only byte operations on the whole WDI register
should be used when writing. The byte must have all
bits set except the bits that are to be cleared.
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