EVAL-ADM1066LFEBZ Analog Devices Inc, EVAL-ADM1066LFEBZ Datasheet - Page 5
![BOARD EVALUATION FOR ADM1066LF](/photos/9/8/90849/eval-adm1066lfeb_board_sml.jpg)
EVAL-ADM1066LFEBZ
Manufacturer Part Number
EVAL-ADM1066LFEBZ
Description
BOARD EVALUATION FOR ADM1066LF
Manufacturer
Analog Devices Inc
Specifications of EVAL-ADM1066LFEBZ
Main Purpose
Power Management, Power Supply Supervisor/Tracker/Sequencer
Embedded
No
Utilized Ic / Part
ADM1066
Primary Attributes
10 Channel Supervisor / Sequencer, 6 Voltage Output DACs
Secondary Attributes
GUI Programmable via SMBus (via USB)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
SPECIFICATIONS
VH = 3.0 V to 14.4 V
Table 1.
Parameter
POWER SUPPLY ARBITRATION
POWER SUPPLY
SUPPLY FAULT DETECTORS
ANALOG-TO-DIGITAL CONVERTER
VH, VPx
VPx
VH
VDDCAP
C
Supply Current, I
Additional Currents
DAC Supply Currents
ADC Supply Current
EEPROM Erase Current
VH Pin
VPx Pins
VXx Pins
Absolute Accuracy
Threshold Resolution
Digital Glitch Filter
Signal Range
Input Reference Voltage on
Resolution
INL
Gain Error
VDDCAP
All PDO FET Drivers On
Input Impedance
Input Attenuator Error
Detection Ranges
Input Impedance
Input Attenuator Error
Detection Ranges
Input Impedance
Detection Range
REFIN Pin, V
Current Available from
High Range
Midrange
Midrange
Low Range
Ultralow Range
Ultralow Range
VDDCAP
REFIN
VH
, I
1
VPx
, VPx = 3.0 V to 6.0 V
Min
3.0
2.7
10
6
2.5
2.5
1.25
0.573
1
0.573
0
1
, T
A
Typ
4.75
4.2
1
2.2
1
10
52
±0.05
52
±0.05
8
0
100
2.048
12
= −40°C to +85°C, unless otherwise noted.
Max
6.0
14.4
5.4
6
2
14.4
6
6
3
1.375
1.375
±1
V
±2.5
±0.05
REFIN
Rev. D | Page 5 of 32
Unit
V
V
V
V
μF
mA
mA
mA
mA
mA
mA
kΩ
%
V
V
kΩ
%
V
V
V
MΩ
V
%
Bits
μs
μs
V
V
Bits
LSB
%
Test Conditions/Comments
Minimum supply required on one of VPx, VH
Maximum VDDCAP = 5.1 V, typical
VDDCAP = 4.75 V
Regulated LDO output
Minimum recommended decoupling capacitance
VDDCAP = 4.75 V, PDO1 to PDO10 off, DACs off, ADC off
VDDCAP = 4.75 V, PDO1 to PDO6 loaded with 1 μA each,
PDO7 to PDO10 off
Maximum additional load that can be drawn from all PDO
pull-ups to VDDCAP
Six DACs on with 100 μA maximum load on each
Running round-robin loop
1 ms duration only, VDDCAP = 3 V
Midrange and high range
Low range and midrange
No input attenuation error
No input attenuation error
VREF error + DAC nonlinearity + comparator offset error + input
attenuation error
Minimum programmable filter length
Maximum programmable filter length
The ADC can convert signals presented to the VH, VPx, and VXx
pins; VPx and VH input signals are attenuated depending on the
selected range; a signal at the pin corresponding to the selected
range is from 0.573 V to 1.375 V at the ADC input
Endpoint corrected, V
V
REFIN
= 2.048 V
REFIN
= 2.048 V
ADM1066