EA-XPR-001 Embedded Artists, EA-XPR-001 Datasheet - Page 19

• Manufacturer Part Number: EA-XPR-001
• Description: BOARD LPCXPRESSO LPC1343
• Manufacturer: Embedded Artists
• Series: LPCXpressor
• Type: MCUr

Specifications of EA-XPR-001

• Contents: Board, Software
• For Use With/related Products: EA-XPR-021, ARM Cortex-M3
• For Use With: EA-XPR-021 - BOARD BASE LPCXPRESSO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
LPC1311_13_42_43
Product data sheet
7.9.1.1 Features
7.9.1 Full-speed USB device controller
7.10 UART
7.9 USB interface (LPC1342/43 only)
The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a
host and one or more (up to 127) peripherals. The host controller allocates the USB
bandwidth to attached devices through a token-based protocol. The bus supports
hot-plugging and dynamic configuration of the devices. All transactions are initiated by the
host controller.
The LPC1342/43 USB interface is a device controller with on-chip PHY for device
functions.
The device controller enables 12 Mbit/s data exchange with a USB Host controller. It
consists of a register interface, serial interface engine, and endpoint buffer memory. The
serial interface engine decodes the USB data stream and writes data to the appropriate
endpoint buffer. The status of a completed USB transfer or error condition is indicated via
status registers. An interrupt is also generated if enabled.
Table 5.
The LPC1311/13/42/43 contains one UART.
Support for RS-485/9-bit mode allows both software address detection and automatic
address detection using 9-bit mode.
Logical
endpoint
0
0
1
1
2
2
3
3
4
4
•
•
•
•
•
•
Dedicated USB PLL available.
Fully compliant with USB 2.0 specification (full speed).
Supports 10 physical (5 logical) endpoints with up to 64 bytes buffer RAM per
endpoint (see
Supports Control, Bulk, Isochronous, and Interrupt endpoints.
Supports SoftConnect feature.
Double buffer implementation for Bulk and Isochronous endpoints.
USB device endpoint configuration
Physical
endpoint
0
1
2
3
4
5
6
7
8
9
All information provided in this document is subject to legal disclaimers.
Table
Rev. 3 — 10 August 2010
Endpoint type
Control
Control
Interrupt/Bulk
Interrupt/Bulk
Interrupt/Bulk
Interrupt/Bulk
Interrupt/Bulk
Interrupt/Bulk
Isochronous
Isochronous
5).
Direction
out
in
out
in
out
in
out
in
out
in
32-bit ARM Cortex-M3 microcontroller
LPC1311/13/42/43
Packet size
(byte)
64
64
64
64
64
64
64
64
512
512
© NXP B.V. 2010. All rights reserved.
Double buffer
no
no
no
no
no
no
yes
yes
yes
yes
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