EA-XPR-002 Embedded Artists, EA-XPR-002 Datasheet
EA-XPR-002
Specifications of EA-XPR-002
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EA-XPR-002 Summary of contents
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... The peripheral complement of the LPC1111/12/13/14 includes flash memory data memory, one Fast-mode Plus I RS-485/EIA-485 UART two SPI interfaces with SSP features, four general purpose counter/timers, a 10-bit ADC, and general purpose I/O pins. Remark: The LPC1111/12/13/14 series consists of the LPC1100 series (parts LPC111x/101/201/301) and the LPC1100L series (parts LPC111x/102/202/302) ...
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... ADC with input multiplexing among 8 pins. Serial interfaces: UART with fractional baud rate generation, internal FIFO, and RS-485 support. Two SPI controllers with SSP features and with FIFO and multi-protocol capabilities (second SPI on LQFP48 and PLCC44 packages only). I data rate of 1 Mbit/s with multiple address recognition and monitor mode. ...
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... LQFP48: plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm LQFP48: plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm LQFP48: plastic low profile quad flat package; 48 leads; body 7 × 7 × ...
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NXP Semiconductors 4.1 Ordering options Table 2. Ordering options Type number Series LPC1111 LPC1111FHN33/101 LPC1100 LPC1111FHN33/102 LPC1100L LPC1111FHN33/201 LPC1100 LPC1111FHN33/202 LPC1100L LPC1112 LPC1112FHN33/101 LPC1100 LPC1112FHN33/102 LPC1100L LPC1112FHN33/201 LPC1100 LPC1112FHN33/202 LPC1100L LPC1113 LPC1113FHN33/201 LPC1100 LPC1113FHN33/202 LPC1100L LPC1113FHN33/301 LPC1100 LPC1113FHN33/302 LPC1100L LPC1113FBD48/301 ...
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NXP Semiconductors 5. Block diagram LPC1111/12/13/14 HIGH-SPEED GPIO ports GPIO PIO0/1/2/3 RXD TXD (1) DTR, DSR , CTS, (1) (1) DCD , RI , RTS CT32B0_MAT[3:0] 32-bit COUNTER/TIMER 0 CT32B0_CAP0 CT32B1_MAT[3:0] 32-bit COUNTER/TIMER 1 CT32B1_CAP0 CT16B0_MAT[2:0] 16-bit COUNTER/TIMER 0 CT16B0_CAP0 ...
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NXP Semiconductors 6. Pinning information 6.1 Pinning PIO2_6 PIO2_0/DTR/SSEL1 RESET/PIO0_0 PIO0_1/CLKOUT/CT32B0_MAT2 V XTALIN XTALOUT V PIO1_8/CT16B1_CAP0 PIO0_2/SSEL0/CT16B0_CAP0 PIO2_7 PIO2_8 Fig 2. Pin configuration LQFP48 package LPC1111_12_13_14 Product data sheet LPC1113FBD48/301 6 LPC1113FBD48/302 LPC1114FBD48/301 7 ...
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NXP Semiconductors RESET/PIO0_0 PIO0_1/CLKOUT/CT32B0_MAT2 XTALIN XTALOUT V PIO1_8/CT16B1_CAP0 PIO0_2/SSEL0/CT16B0_CAP0 PIO2_7 PIO2_8 PIO2_1/DSR/SCK1 Fig 3. Pin configuration PLCC44 package LPC1111_12_13_14 Product data sheet LPC1114FA44/301 12 DD LPC1114FA44/302 All information ...
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... NXP Semiconductors PIO2_0/DTR RESET/PIO0_0 PIO0_1/CLKOUT/CT32B0_MAT2 PIO1_8/CT16B1_CAP0 PIO0_2/SSEL0/CT16B0_CAP0 Fig 4. Pin configuration HVQFN 33 package LPC1111_12_13_14 Product data sheet terminal 1 index area XTALIN XTALOUT Transparent top view All information provided in this document is subject to legal disclaimers. Rev. 4 — 10 February 2011 LPC1111/12/13/14 32-bit ARM Cortex-M0 microcontroller ...
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... Reset Description state [1] I/O Port 0 — Port 12-bit I/O port with individual direction and function controls for each bit. The operation of port 0 pins depends on the function selected through the IOCONFIG register block RESET — External reset input with 20 ns glitch filter. A ...
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... O - CT32B0_MAT3 — Match output 3 for 32-bit timer 0. I/O Port 1 — Port 12-bit I/O port with individual direction and function controls for each bit. The operation of port 1 pins depends on the function selected through the IOCONFIG register block — Reserved. Configure for an alternate function in the IOCONFIG block ...
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... I - AD7 — A/D converter, input 7. I/O Port 2 — Port 12-bit I/O port with individual direction and function controls for each bit. The operation of port 2 pins depends on the function selected through the IOCONFIG register block. I PIO2_0 — General purpose digital input/output pin. ...
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... SCK0 — Serial clock for SPI0. I/O Port 3 — Port 12-bit I/O port with individual direction and function controls for each bit. The operation of port 3 pins depends on the function selected through the IOCONFIG register block. Pins PIO3_6 to PIO3_11 are not available. ...
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... Description state [1] I/O Port 0 — Port 12-bit I/O port with individual direction and function controls for each bit. The operation of port 0 pins depends on the function selected through the IOCONFIG register block RESET — External reset input with 20 ns glitch filter. A LOW-going ...
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... O - CT32B0_MAT3 — Match output 3 for 32-bit timer 0. Port 1 — Port 12-bit I/O port with individual direction and function controls for each bit. The operation of port 1 pins depends on the function selected through the IOCONFIG register block — Reserved. Configure for an alternate function in the IOCONFIG block ...
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... AD7 — A/D converter, input 7. I/O Port 2 — Port 12-bit I/O port with individual direction and function controls for each bit. The operation of port 2 pins depends on the function selected through the IOCONFIG register block. I PIO2_0 — General purpose digital input/output pin. ...
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... Description state [1] Port 0 — Port 12-bit I/O port with individual direction and function controls for each bit. The operation of port 0 pins depends on the function selected through the IOCONFIG register block. I I;PU RESET — External reset input with 20 ns glitch filter. A LOW-going ...
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... O - CT32B0_MAT3 — Match output 3 for 32-bit timer 0. Port 1 — Port 12-bit I/O port with individual direction and function controls for each bit. The operation of port 1 pins depends on the function selected through the IOCONFIG register block. - I;PU R — Reserved. Configure for an alternate function in the IOCONFIG block ...
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... I - AD7 — A/D converter, input 7. Port 2 — Port 12-bit I/O port with individual direction and function controls for each bit. The operation of port 2 pins depends on the function selected through the IOCONFIG register block. Pins PIO2_1 to PIO2_11 are not available. I/O I;PU PIO2_0 — ...
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NXP Semiconductors Table 5. LPC1111/12/13/14 pin description table (HVQFN33 package) Symbol Pin Start logic input [3] PIO3_5 [6] XTALIN 4 - [6] XTALOUT [1] Pin state at ...
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... The AHB peripheral area is 2 megabyte in size, and is divided to allow for up to 128 peripherals. The APB peripheral area is 512 kB in size and is divided to allow for peripherals. Each peripheral of either type is allocated 16 kilobytes of space. This allows simplifying the address decoding for each peripheral. ...
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... Nested Vectored Interrupt Controller (NVIC) The Nested Vectored Interrupt Controller (NVIC integral part of the Cortex-M0. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts. 7.5.1 Features • Controls system exceptions and peripheral interrupts. LPC1111_12_13_14 ...
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... Additionally, any GPIO pin (total pins) providing a digital function can be programmed to generate an interrupt on a level, a rising or falling edge, or both. 7.7.1 Features • Bit level port registers allow a single instruction to set or clear any number of bits in one write operation. • Direction control of individual bits. ...
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... The I C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock Line (SCL) and a Serial DAta line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver transmitter with the capability to both receive and send information (such as memory). Transmitters and/or ...
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... The counter/timer is designed to count cycles of the system derived clock. It can optionally generate interrupts or perform other actions at specified timer values, based on four match registers. Each counter/timer also includes one capture input to trap the timer value when an input signal transitions, optionally generating an interrupt. ...
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... Watchdog operation under different power reduction conditions. It also provides the ability to run the WDT from an entirely internal source that is not dependent on an external crystal and its associated components and wiring for increased reliability. LPC1111_12_13_14 Product data sheet × 256 × cy(WDCLK) × ...
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... Crystal oscillators The LPC1111/12/13/14 include three independent oscillators. These are the system oscillator, the Internal RC oscillator (IRC), and the Watchdog oscillator. Each oscillator can be used for more than one purpose as required in a particular application. Following reset, the LPC1111/12/13/14 will operate from the Internal RC oscillator until switched by software ...
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... MHz IRC oscillator as the clock source. This allows chip operation to resume quickly. If the system oscillator or the PLL is needed by the application, software will need to enable these features and wait for them to stabilize before they are used as a clock source. ...
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NXP Semiconductors peripherals, allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. Selected peripherals have their own clock divider which provides even better power control. 7.15.5.1 Power ...
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... BOD asserts an interrupt signal to the NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a dedicated status register. Four additional threshold levels can be selected to cause a forced reset of the chip ...
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... IAP calls or call reinvoke ISP command to enable flash update via the UART. CAUTION If level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device. In addition to the three CRP levels, sampling of pin PIO0_1 for valid user code can be disabled ...
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... The following applies to the limiting values: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V otherwise noted ...
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NXP Semiconductors 9. Static characteristics Table 7. Static characteristics = −40 °C to +85 °C, unless otherwise specified. T amb Symbol Parameter V supply voltage (core DD and external rail) LPC1100 series (LPC111x/101/201/301) power consumption I supply current DD LPC1100L ...
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NXP Semiconductors Table 7. Static characteristics = −40 °C to +85 °C, unless otherwise specified. T amb Symbol Parameter V input voltage I V output voltage O V HIGH-level input IH voltage V LOW-level input voltage IL V hysteresis voltage ...
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... V HIGH-level input IH voltage V LOW-level input voltage IL V hysteresis voltage hys I LOW-level output OL current I LOW-level output OL current I input leakage current LI Oscillator pins V crystal input voltage i(xtal) V crystal output voltage o(xtal) LPC1111_12_13_14 Product data sheet …continued Conditions 2.5 V ≤ V ≤ 3 − 1.8 V ≤ V < ...
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... R i LPC1111_12_13_14 Product data sheet Conditions ) is the difference between the actual step width and the ideal step width. See ) is the peak difference between the center of the steps of the actual and the ideal transfer curve after Figure 7. Figure Figure 7. ...
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... E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (E (4) Integral non-linearity (E L(adj) (5) Center of a step of the actual transfer curve. Fig 7. ADC characteristics LPC1111_12_13_14 Product data sheet (2) (5) (4) (3) 1 LSB (ideal (LSB ...
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... Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see LPC111x user manual. 9.2 Power consumption LPC111x/101/201/301 Power measurements in Active, Sleep, and Deep-sleep modes were performed under the following conditions (see LPC111x user manual): • Configure all pins as GPIO with pull-up resistor disabled in the IOCONFIG block. ...
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NXP Semiconductors (mA) (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 8. (mA) (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; ...
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NXP Semiconductors (mA) (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 10. Sleep mode: Typical supply current I (μA) Fig 11. Deep-sleep mode: Typical supply current I LPC1111_12_13_14 Product ...
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... Fig 12. Deep power-down mode: Typical supply current I 9.3 Power consumption LPC111x/102/202/302 Power measurements in Active, Sleep, and Deep-sleep modes were performed under the following conditions (see LPC111x user manual): • Configure all pins as GPIO with pull-up resistor disabled in the IOCONFIG block. ...
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NXP Semiconductors (mA) (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 13. Active mode: Typical supply current I (mA) (1) System oscillator and system PLL disabled; IRC enabled. (2) ...
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NXP Semiconductors (mA) (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 15. Sleep mode: Typical supply current I LPC1111_12_13_14 Product data sheet −40 ...
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NXP Semiconductors (μA) Fig 16. Deep-sleep mode: Typical supply current I (μA) Fig 17. Deep power-down mode: Typical supply current I LPC1111_12_13_14 Product data sheet 5 4.5 3 3 2.5 1.5 −40 ...
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... NXP Semiconductors 9.4 Peripheral power consumption The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG and PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both registers and no code is executed. Measured on a typical sample at T noted otherwise, the system oscillator and PLL are running in both measurements ...
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NXP Semiconductors 9.5 Electrical pin characteristics V Fig 18. High-drive output: Typical HIGH-level output voltage V (mA) Fig 19. I LPC1111_12_13_14 Product data sheet 3 °C (V) 25 °C −40 °C 3.2 2.8 2 ...
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NXP Semiconductors (mA) Fig 20. Typical LOW-level output current I V Fig 21. Typical HIGH-level output voltage V LPC1111_12_13_14 Product data sheet 0.2 Conditions 3.3 V; standard port pins and PIO0_7. ...
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NXP Semiconductors (μA) Fig 22. Typical pull-up current I (μA) Fig 23. Typical pull-down current I LPC1111_12_13_14 Product data sheet −10 − °C 25 °C −40 °C −50 − Conditions ...
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... Rev. 4 — 10 February 2011 LPC1111/12/13/14 32-bit ARM Cortex-M0 microcontroller Min Typ ≤ 400 mV [ [1][ wait 002aag001 ) 1 Min Typ [1] 10000 100000 100 [2] 0.95 1 Max Unit 500 ms μs - 400 mV Max Unit - cycles - years - years 105 ms 1.05 ms © NXP B.V. 2011. All rights reserved ...
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... Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply [2] voltages. Fig 25. External clock timing (with an amplitude of at least V LPC1111_12_13_14 Product data sheet Dynamic characteristic: external clock over specified ranges ...
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... Symbol Parameter f osc(int) Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply [1] voltages. [2] The typical frequency spread over processing and temperature (T [3] See the LPC111x user manual. LPC1111_12_13_14 Product data sheet Dynamic characteristic: internal oscillators ≤ 3.6 V. ...
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... Parameters are valid over operating temperature range unless otherwise specified. [3] t HD;DAT and the acknowledge. [4] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the V (min) of the SCL signal) to bridge the undefined region of the falling edge of SCL total capacitance of one bus line in pF ...
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... UM10204). This maximum must only be met if VD;DAT VD;ACK is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in 2 C-bus device can be used in a Standard-mode I = 250 ns must then be met. This will automatically be the case if the device does not stretch the ...
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NXP Semiconductors Table 18. Dynamic characteristics of SPI pins in SPI mode Symbol Parameter T PCLK cycle time cy(PCLK) t data set-up time DS t data hold time DH t data output valid time in SPI mode v(Q) t data ...
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NXP Semiconductors SCK (CPOL = 0) SCK (CPOL = 1) Fig 29. SPI slave timing in SPI mode LPC1111_12_13_14 Product data sheet T cy(clk) MOSI DATA VALID t MISO DATA VALID MOSI DATA VALID t v(Q) MISO DATA VALID Pin ...
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... C mode, a minimum of 200 mV (RMS) is needed. Fig 30. Slave mode operation of the on-chip oscillator In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF (Figure corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V. The XTALOUT pin in this configuration can be left unconnected. ...
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NXP Semiconductors Fig 31. Oscillator modes and models: oscillation mode of operation and external crystal Table 19. Fundamental oscillation frequency F 1 MHz - 5 MHz 5 MHz - 10 MHz 10 MHz - 15 MHz 15 MHz - 20 ...
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... NXP Semiconductors order to keep the noise coupled in via the PCB as small as possible. Also parasitics should stay as small as possible. Values of C accordingly to the increase in parasitics of the PCB layout. 11.4 Standard I/O pad configuration Figure 32 • Digital output driver • Digital input: Pull-up enabled/disabled • ...
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... NXP Semiconductors 11.5 Reset pad configuration Fig 33. Reset pad configuration 11.6 ElectroMagnetic Compatibility (EMC) Radiated emission measurements according to the IEC61967-2 standard using the TEM-cell method are shown for the LPC1114FBD48/302 in Table 21 3 Parameter Input clock: IRC (12 MHz) maximum peak level IEC level ...
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... NXP Semiconductors 12. Package outline LQFP48: plastic low profile quad flat package; 48 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.20 1.45 1.6 mm 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION ...
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... NXP Semiconductors PLCC44: plastic leaded chip carrier; 44 leads pin 1 index 6 β DIMENSIONS (mm dimensions are derived from the original inch dimensions UNIT max. min. 4.57 0.53 mm 0.51 0.25 3.05 4.19 0.33 0.180 0.021 inches 0.02 0.01 0.12 0.165 0.013 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...
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... NXP Semiconductors HVQFN33: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 0.85 mm terminal 1 index area terminal 1 32 index area Dimensions (1) Unit max 1.00 0.05 0.35 mm nom 0.85 0.02 0.28 0.2 min 0.80 0.00 0.23 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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NXP Semiconductors 13. Abbreviations Table 22. Acronym ADC AHB APB BOD GPIO PLL RC SPI SSI SSP TEM UART LPC1111_12_13_14 Product data sheet Abbreviations Description Analog-to-Digital Converter Advanced High-performance Bus Advanced Peripheral Bus BrownOut Detection General Purpose Input/Output Phase-Locked Loop ...
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... NXP Semiconductors 14. Revision history Table 23. Revision history Document ID Release date LPC1111_12_13_14 v.4 20110210 Modifications: LPC1111_12_13_14 v.3 20101110 Modifications: LPC1111_12_13_14 v.2 20100818 Modifications: LPC1111_12_13_14 v.1 20100416 LPC1111_12_13_14 Product data sheet Data sheet status Product data sheet • Power consumption graphs added for parts LPC111x/102/202/302 Figure 17) ...
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... NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’ ...
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... NXP Semiconductors’ specifications such use shall be solely at customer’s 16. Contact information For more information, please visit: For sales office addresses, please send an email to: LPC1111_12_13_14 Product data sheet own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.8 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.8.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.9 SPI serial I/O controller 7.9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2 7.10 I C-bus serial I/O controller . . . . . . . . . . . . . . 23 7.10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.11 10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.12 General purpose external event counter/timers . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.13 System tick timer . . . . . . . . . . . . . . . . . . . . . . 25 7.14 Watchdog timer 7.14.1 Features ...