EA-XPR-007 Embedded Artists, EA-XPR-007 Datasheet
EA-XPR-007
Specifications of EA-XPR-007
Related parts for EA-XPR-007
EA-XPR-007 Summary of contents
Page 1
... The LPC11U1x operate at CPU frequencies MHz. Equipped with a highly flexible and configurable Full Speed USB 2.0 device controller, the LPC11U1x brings unparalleled design flexibility and seamless integration to today's demanding connectivity solutions. The peripheral complement of the LPC11U1x includes flash memory SRAM data memory, one Fast-mode Plus I USART with support for synchronous mode and smart card interface, two SSP interfaces, four general purpose counter/timers, a 10-bit ADC, and general purpose I/O pins ...
Page 2
NXP Semiconductors Two GPIO grouped interrupt modules enable an interrupt based on a programmable pattern of input states of a group of GPIO pins. High-current source output driver (20 mA) on one pin (P0_7). High-current sink driver ...
Page 3
... plastic low profile quad flat package; 48 leads; body 7 7 1.4 mm plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 7 0.85 mm plastic low profile quad flat package; 48 leads; body 7 7 1.4 mm plastic thin fine-pitch ball grid array package; 48 balls; body 4.5 4.5 0.7 mm ...
Page 4
NXP Semiconductors 5. Block diagram LPC11U12/13/14 system bus HIGH-SPEED GPIO ports 0/1 GPIO RXD TXD (1) (1) (1) DCD , DSR , RI SMARTCARD INTERFACE CTS, RTS, DTR SCLK CT16B0_MAT[1:0] 16-bit COUNTER/TIMER 0 CT16B0_CAP0 CT16B1_MAT[1:0] 16-bit COUNTER/TIMER 1 CT16B1_CAP0 CT32B0_MAT[3:0] ...
Page 5
... NXP Semiconductors 6. Pinning information 6.1 Pinning PIO1_19/DTR/SSEL1 PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE PIO0_20/CT16B1_CAP0 PIO0_2/SSEL0/CT16B0_CAP0 Fig 2. Pin configuration (HVQFN33) LPC11U1X Objective data sheet terminal 1 index area 1 RESET/PIO0_0 2 3 XTALIN 4 LPC11U1x XTALOUT Transparent top view All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 April 2011 ...
Page 6
NXP Semiconductors PIO1_25/CT32B0_MAT1 PIO1_19/DTR/SSEL1 RESET/PIO0_0 PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE XTALIN XTALOUT PIO0_20/CT16B1_CAP0 PIO0_2/SSEL0/CT16B0_CAP0 PIO1_26/CT32B0_MAT2/RXD PIO1_27/CT32B0_MAT3/TXD Fig 3. Pin configuration (LQFP48) LPC11U1X Objective data sheet LPC11U1x All information ...
Page 7
... NXP Semiconductors Fig 4. Pin configuration (TFBGA48) LPC11U1X Objective data sheet ball A1 LPC11U1x index area Transparent top view All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 April 2011 LPC11U1x 32-bit ARM Cortex-M0 microcontroller 002aag101 © NXP B.V. 2011. All rights reserved. ...
Page 8
... PIO0_4 and PIO0_5. Every port pin has a corresponding IOCON register through which the digital or analog function, pull-up/pull-down configuration, repeater, and open-drain modes can be programmed. The USART, counter/timer, and SSP functions are available on more than one port pin. ...
Page 9
... Used with the SoftConnect USB feature. SCK0 — Serial clock for SSP0. PIO0_7 — General purpose digital input/output pin (high-current output driver). CTS — Clear To Send input for USART. PIO0_8 — General purpose digital input/output pin. MISO0 — Master In Slave Out for SSP0. ...
Page 10
NXP Semiconductors Table 3. Pin description Symbol TMS/PIO0_12/AD1/ 22 CT32B1_CAP0 TDO/PIO0_13/AD2/ 23 CT32B1_MAT0 TRST/PIO0_14/AD3/ 24 CT32B1_MAT1 SWDIO/PIO0_15/AD4/ 25 CT32B1_MAT2 PIO0_16/AD5/ 26 CT32B1_MAT3/WAKEUP PIO0_17/RTS/ 30 CT32B0_CAP0/SCLK LPC11U1X Objective data sheet Reset Type state [1] [ ...
Page 11
NXP Semiconductors Table 3. Pin description Symbol PIO0_18/RXD/ 31 CT32B0_MAT0 PIO0_19/TXD/ 32 CT32B0_MAT1 PIO0_20/CT16B1_CAP0 7 PIO0_21/CT16B1_MAT0/ 12 MOSI1 PIO0_22/AD6/ 20 CT16B1_MAT1/MISO1 PIO0_23/AD7 27 PIO1_0/CT32B1_MAT0 - PIO1_1/CT32B1_MAT1 - PIO1_2/CT32B1_MAT2 - LPC11U1X Objective data sheet Reset Type state [1] [ ...
Page 12
... TXD — Transmitter output for USART. PIO1_14 — General purpose digital input/output pin. DSR — Data Set Ready input for USART. CT16B0_MAT1 — Match output 1 for 16-bit timer 0. RXD — Receiver input for USART. © NXP B.V. 2011. All rights reserved. ...
Page 13
... DTR — Data Terminal Ready output for USART. SSEL1 — Slave select for SSP1. PIO1_20 — General purpose digital input/output pin. DSR — Data Set Ready input for USART. SCK1 — Serial clock for SSP1. PIO1_21 — General purpose digital input/output pin. ...
Page 14
NXP Semiconductors Table 3. Pin description Symbol PIO1_23/CT16B1_MAT1/ - SSEL1 PIO1_24/CT32B0_MAT0 - PIO1_25/CT32B0_MAT1 - PIO1_26/CT32B0_MAT2/ - RXD PIO1_27/CT32B0_MAT3/ - TXD PIO1_28/CT32B0_CAP0/ - SCLK PIO1_29/SCK0/ - CT32B0_CAP1 PIO1_31 - USB_DM 13 USB_DP 14 XTALIN 4 LPC11U1X Objective data sheet Reset Type ...
Page 15
NXP Semiconductors Table 3. Pin description Symbol XTALOUT [1] Pin state at reset for default function Input Output internal pull-up enabled inactive, no pull-up/down ...
Page 16
NXP Semiconductors Table 4. Peripheral SSP0 SSP1 CT16B0 CT16B1 CT32B0 CT32B1 ADC USB CLKOUT LPC11U1X Objective data sheet Multiplexing of peripheral functions Function Type Default Available on ports SCK0 I/O no SSEL0 I/O no MISO0 I/O no MOSI0 I/O no ...
Page 17
... Figure 5 program viewpoint following reset. The interrupt vector area supports address remapping. The AHB peripheral area size and is divided to allow for up to 128 peripherals. The APB peripheral area is 512 kB in size and is divided to allow for peripherals. Each peripheral of either type is allocated space. This allows simplifying the address decoding for each peripheral ...
Page 18
... Nested Vectored Interrupt Controller (NVIC) The Nested Vectored Interrupt Controller (NVIC integral part of the Cortex-M0. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts. 7.2.1 Features • Controls system exceptions and peripheral interrupts. • ...
Page 19
... All GPIO pins default to inputs with interrupt disabled at reset. • Pin registers allow pins to be sensed and set individually. • eight GPIO pins can be selected from all GPIO pins to create an edge- or level-sensitive GPIO interrupt request. • Port interrupts can be triggered by any pin or pins in each port. ...
Page 20
... The device controller enables 12 Mbit/s data exchange with a USB Host controller. It consists of a register interface, serial interface engine, and endpoint buffer memory. The serial interface engine decodes the USB data stream and writes data to the appropriate endpoint buffer. The status of a completed USB transfer or error condition is indicated via status registers ...
Page 21
... The I C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock line (SCL) and a Serial Data line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed ...
Page 22
... Do nothing on match. • The timer and prescaler may be configured to be cleared on a designated capture event. This feature permits easy pulse-width measurement by clearing the timer on the leading edge of an input pulse and capturing the timer value on the trailing edge. LPC11U1X Objective data sheet . ...
Page 23
... Integrated oscillators The LPC11U1x include three independent oscillators. These are the system oscillator, the Internal RC oscillator (IRC), and the watchdog oscillator. Each oscillator can be used for more than one purpose as required in a particular application. Following reset, the LPC11U1x will operate from the internal RC oscillator until switched by software ...
Page 24
NXP Semiconductors IRC oscillator watchdog oscillator MAINCLKSEL (main clock select) IRC oscillator SYSTEM PLL system oscillator SYSPLLCLKSEL (system PLL clock select) system oscillator USB PLL USBPLLCLKSEL (USB clock select) Fig 6. LPC11U1x clocking generation block diagram 7.13.1.1 Internal RC oscillator ...
Page 25
... MHz IRC oscillator as the clock source. This allows chip operation to resume quickly. If the main oscillator or the PLL is needed by the application, software will need to enable these features and wait for them to stabilize before they are used as a clock source. ...
Page 26
NXP Semiconductors on-chip peripherals, allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. Selected peripherals have their own clock divider which provides even better power control. 7.13.5.1 ...
Page 27
... BOD asserts an interrupt signal to the NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a dedicated status register. Four additional threshold levels can be selected to cause a forced reset of the chip ...
Page 28
... IAP calls or call reinvoke ISP command to enable flash update via the USART. CAUTION If level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device. In addition to the three CRP levels, sampling of pin PIO0_1 for valid user code can be disabled ...
Page 29
... The following applies to the limiting values: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V otherwise noted ...
Page 30
NXP Semiconductors 9. Static characteristics Table 6. Static characteristics +85 C, unless otherwise specified. amb Symbol Parameter Conditions V supply voltage (core DD and external rail) I supply current Active mode; V ...
Page 31
NXP Semiconductors Table 6. Static characteristics …continued +85 C, unless otherwise specified. amb Symbol Parameter Conditions I LOW-level output V OL current I HIGH-level short-circuit V OHS output current I LOW-level short-circuit ...
Page 32
... IRC enabled; system oscillator disabled; system PLL disabled. [3] I measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled. DD [4] BOD disabled. [5] All peripherals disabled in the AHBCLKCTRL register. Peripheral clocks to USART, SSP0/1 disabled in the syscon block. ...
Page 33
NXP Semiconductors [7] Low-current mode PWR_LOW_CURRENT selected when running the set_power routine in the power profiles. [8] IRC disabled; system oscillator enabled; system PLL enabled. [9] WAKEUP pin pulled HIGH externally. An external pull-up resistor is required on the RESET ...
Page 34
... See D [3] The integral non-linearity ( the peak difference between the center of the steps of the actual and the ideal transfer curve after L(adj) appropriate adjustment of gain and offset errors. See [4] ...
Page 35
... E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error ( (4) Integral non-linearity (E ). L(adj) (5) Center of a step of the actual transfer curve. Fig 7. ADC characteristics LPC11U1X Objective data sheet (2) (5) (4) (3) 1 LSB (ideal) 1018 4 5 ...
Page 36
... Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see LPC11U1x user manual. 9.2 Power consumption Power measurements in Active, Sleep, and Deep-sleep modes were performed under the following conditions (see LPC11U1x user manual): • Configure all pins as GPIO with pull-up resistor disabled in the IOCON block. ...
Page 37
NXP Semiconductors X (X) Conditions: T internal pull-up resistors disabled; system oscillator and system PLL enabled; IRC, BOD disabled; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = <tbd>); all peripheral clocks disabled; USB_DP and USB_DM pulled LOW externally. Fig ...
Page 38
NXP Semiconductors X (X) Conditions: V oscillator and system PLL enabled; IRC, BOD disabled; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = <tbd>); all peripheral clocks disabled; USB_DP and USB_DM pulled LOW externally. Fig 10. Typical supply current versus ...
Page 39
NXP Semiconductors X (X) Conditions: BOD disabled; all oscillators and analog blocks turned off in the PDSLEEPCFG register; PDSLEEPCFG = <tbd>; USB_DP and USB_DM pulled LOW externally. Fig 12. Typical supply current versus temperature in Power-down mode X (X) Fig ...
Page 40
... Table 9. Power consumption for individual analog and digital blocks The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCTRL or PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both registers and no code is executed. Measured on a typical sample at T the system oscillator and PLL are running in both measurements ...
Page 41
NXP Semiconductors 9.3 Electrical pin characteristics 3 (V) 3.2 2.8 2.4 Conditions: V Fig 14. High-drive output: Typical HIGH-level output voltage V output current (mA Conditions: V Fig 15. I LOW-level output ...
Page 42
NXP Semiconductors (mA) 10 Conditions: V Fig 16. Typical LOW-level output current I 3 (V) 3.2 2.8 2.4 Conditions: V Fig 17. Typical HIGH-level output voltage V I LPC11U1X Objective data sheet ...
Page 43
NXP Semiconductors (μA) −10 −30 −50 −70 Conditions: V Fig 18. Typical pull-up current (μ Conditions: V Fig 19. Typical pull-down current I LPC11U1X Objective data sheet ...
Page 44
... Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply [2] voltages. Fig 20. External clock timing (with an amplitude of at least V LPC11U1X Objective data sheet Flash characteristics ...
Page 45
... Fig 21. Internal RC oscillator frequency versus temperature Table 13. Symbol f osc(int) [1] Typical ratings are not guaranteed. The values listed are at nominal supply voltages. [2] The typical frequency spread over processing and temperature (T [3] See the LPC11U1x user manual. LPC11U1X Objective data sheet Dynamic characteristics: IRC ...
Page 46
... Parameters are valid over operating temperature range unless otherwise specified. [3] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge. [4] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the V bridge the undefined region of the falling edge of SCL ...
Page 47
... UM10204). This maximum must only be met if the device does not stretch the LOW period (t VD;ACK SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock. [9] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the acknowledge. 2 [10] A Fast-mode I C-bus device can be used in a Standard-mode I This will automatically be the case if the device does not stretch the LOW period of the SCL signal ...
Page 48
NXP Semiconductors 10.6 SSP interface Table 16. Dynamic characteristics: SSP pins in SPI mode Symbol Parameter SSP master T clock cycle time cy(clk) t data set-up time DS t data hold time DH t data output valid time v(Q) t ...
Page 49
NXP Semiconductors SCK (CPOL = 0) SCK (CPOL = 1) Fig 23. SSP master timing in SPI mode LPC11U1X Objective data sheet T cy(clk) t v(Q) DATA VALID MOSI DATA VALID MISO t v(Q) DATA VALID DATA VALID MOSI t ...
Page 50
NXP Semiconductors SCK (CPOL = 0) SCK (CPOL = 1) Fig 24. SSP slave timing in SPI mode LPC11U1X Objective data sheet T cy(clk) MOSI DATA VALID t v(Q) MISO DATA VALID t DS MOSI DATA VALID DATA VALID t ...
Page 51
NXP Semiconductors 10.7 USB interface Table 17. Dynamic characteristics: USB pins (full-speed) pF 1 Symbol Parameter t rise time r t fall time f t differential rise ...
Page 52
NXP Semiconductors 11. Application information 11.1 Suggested USB interface solutions LPC11U1x Fig 26. USB interface on a self-powered device LPC11U1x Fig 27. USB interface on a bus-powered device 11.2 XTAL input The input voltage to the on-chip oscillators is limited ...
Page 53
... NXP Semiconductors Fig 28. Slave mode operation of the on-chip oscillator In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF (Figure 28), with an amplitude between 200 mV(RMS) and 1000 mV(RMS). This corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V. ...
Page 54
... Loops must be made as small as possible in order to keep the noise coupled in via the PCB as small as possible. Also parasitics should stay as small as possible. Values of C accordingly to the increase in parasitics of the PCB layout. LPC11U1X Objective data sheet Recommended values for C ...
Page 55
... Standard I/O pad configuration Figure 30 • Digital output driver • Digital input: Pull-up enabled/disabled • Digital input: Pull-down enabled/disabled • Digital input: Repeater mode enabled/disabled • Analog input pin configured as digital output driver pin configured as digital input pin configured as analog input Fig 30 ...
Page 56
... Reset pad configuration reset Fig 31. Reset pad configuration 11.6 ADC usage notes The following guidelines show how to increase the performance of the ADC in a noisy environment beyond the ADC specifications listed in • The ADC input trace must be short and as close as possible to the LPC11U1x chip. ...
Page 57
... NXP Semiconductors 12. Package outline HVQFN33: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 0.85 mm terminal 1 index area terminal 1 32 index area Dimensions (1) Unit max 1.00 0.05 0.35 7.1 mm nom 0.85 0.02 0.28 0.2 7.0 min 0.80 0.00 0.23 6 ...
Page 58
... NXP Semiconductors LQFP48: plastic low profile quad flat package; 48 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.20 1.45 0.27 1.6 mm 0.25 0.05 1.35 0.17 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION ...
Page 59
... NXP Semiconductors TFBGA48: plastic thin fine-pitch ball grid array package; 48 balls; body 4.5 x 4.5 x 0.7 mm ball A1 index area ball index area Dimensions Unit max 1.10 0.30 0.80 0.35 4.6 mm nom 0.95 0.25 0.70 0.30 4.5 min 0.85 0.20 0.65 0.25 4.4 ...
Page 60
NXP Semiconductors 13. Abbreviations Table 20. Acronym A/D ADC AHB APB BOD GPIO JTAG PLL RC SPI SSI SSP TAP USART LPC11U1X Objective data sheet Abbreviations Description Analog-to-Digital Analog-to-Digital Converter Advanced High-performance Bus Advanced Peripheral Bus BrownOut Detection General Purpose ...
Page 61
... NXP Semiconductors 14. Revision history Table 21. Revision history Document ID Release date LPC11U1X v.1 20110411 LPC11U1X Objective data sheet Data sheet status Change notice Objective data sheet - All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 April 2011 LPC11U1x 32-bit ARM Cortex-M0 microcontroller ...
Page 62
... NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’ ...
Page 63
... NXP Semiconductors’ specifications such use shall be solely at customer’s 16. Contact information For more information, please visit: For sales office addresses, please send an email to: LPC11U1X Objective data sheet own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
Page 64
... USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.6.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.7 SSP serial I/O controller . . . . . . . . . . . . . . . . . 21 7.7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2 7.8 I C-bus serial I/O controller . . . . . . . . . . . . . . 21 7.8.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.9 10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.10 General purpose external event counter/timers . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.11 System tick timer . . . . . . . . . . . . . . . . . . . . . . 23 7.12 Windowed WatchDog Timer (WWDT ...