AD6636BC/PCB Analog Devices Inc, AD6636BC/PCB Datasheet - Page 54

• Manufacturer Part Number: AD6636BC/PCB
• Description: BOARD EVAL FOR AD6636
• Manufacturer: Analog Devices Inc

Specifications of AD6636BC/PCB

• Rohs Status: RoHS non-compliant
• Module/board Type: Evaluation Board
• For Use With/related Products: AD6636
• Lead Free Status / Rohs Status: Not Compliant

AD6636
SPORT Mode Timing
In SPORT mode, the SCLK continuously runs, and the external
SRFS and STFS signals are used to frame the data. Incoming
framing signals SRFS (receive) and STFS (transmit) are sampled
on the falling edges of SCLK. All input and output data must be
transmitted or received in 8-bit segments starting with the
rising edge after SRFS or STFS is sampled.
MSBFIRST
MSBFIRST
SMODE
SMODE
MODE
MODE
SCLK
SRFS
SCLK
SRFS
STFS
STFS
SDO
SDO
SCS
SCS
SDI
SDI
A0
A7
A1
A6
BLOCK START ADDRESS
BLOCK START ADDRESS
A2
A5
A3
A4
A4
A3
A5
A2
A6
A1
A7
A0
Figure 52. SPORT Write MSB_FIRST = 1
Figure 53. SPORT Write MSB_FIRST = 0
WRITE
N0
0
Rev. A | Page 54 of 80
N1
N6
BLOCK COUNT (Nx)
N2
N5
BLOCK COUNT (Nx)
N3
N4
SPORT Write
Serial data is sampled on the rising edge of SCLK. The data
should be MSB or LSB first, depending on the polarity of the
MSB_FIRST pin. The serial port begins to sample data on the
rising edge of SCLK after SRFS is detected on the falling edge of
SCLK. Once all 8 bits of one byte are shifted in, the data is
transferred to the internal bus.
N4
N3
N5
N2
N6
N1
WRITE
N0
0
D0
D7
D1
D6
D2
D5
D3
D4
D4
D3
D5
D2
D6
D1
D7
D0