ATA5773-DK1 Atmel, ATA5773-DK1 Datasheet - Page 153

• Manufacturer Part Number: ATA5773-DK1
• Description: BOARD XMITTER FOR ATA5773 315MHZ
• Manufacturer: Atmel
• Type: Transmitterr

Specifications of ATA5773-DK1

• Frequency: 315MHz
• Maximum Frequency: 315 MHz
• Supply Voltage (max): 4 V
• Supply Voltage (min): 2 V
• Supply Current: 9 mA
• Product: RF Development Tools
• For Use With/related Products: ATA5773
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9137E–RKE–12/10
• Bits 5:0 – MUX5:0: Analog Channel and Gain Selection Bits
The value of these bits selects which combination of analog inputs are connected to the ADC.
In case of differential input , gain selection is also made with these bits. Selections on
4-51
the offset calibration selections are located. Selecting the single-ended channel ADC8
enables the temperature measurement. See
during a conversion, the change will not go into effect until this conversion is complete (ADIF
in ADCSRA is set).
Table 4-51.
Notes:
See
well as selections of offset calibration channels. MUX0 bit works as a gain selection bit for dif-
ferential channels shown in
selected and when it is set (‘1’) 20x gain is selected. For normal differential channel pairs
MUX5 bit work as a polarity reversal bit. Togling of the MUX5 bit exhanges the positive and
negative channel other way a round.
For offset calibration purpose the offset of the certain differential channels can be measure by
selecting the same input for both negative and positive input. This calibration can be done for
ADC0, ADC3 and ADC7.
bration in a more detailed level.
Table 4-52 on page 154
show values for single endid channels and where the the differential channels as well as
1. See
2.
3. For offset calibration only .See
Reserved for reversal differential channels
Section 4.20.9 “Temperature Measurement” on page 151
on page 141
Reserved for differential channels
Single Endid Input channel Selections.
Reserved for offset calibration
Table 4-52 on page 154
Single Ended Input
ADC0 (PA0)
ADC1 (PA1)
ADC2 (PA2)
ADC3 (PA3)
ADC4 (PA4)
ADC5 (PA5)
ADC6 (PA6)
ADC7 (PA7)
0V (AGND)
1.1V (I Ref)
ADC8
Section 4.20.3 “ADC Operation” on page 141
Table 4-52 on page
for details of selections of differential input channel selections as
(2)
for details.
Table 4-52 on page 154
(3)
(1)
Table 4-51
(1)
154. When MUX0 bit is cleared (‘0’) 1x gain is
Atmel ATA5771/73/74
for details. If these bits are changed
and
Section 4.20.3 “ADC Operation”
001000 - 011111
100011 - 100111
101000 - 111111
MUX5..0
describes offset cali-
000000
000001
000010
000011
000100
000101
000110
000111
100000
100001
100010
Table
153