ATA5773-DK1 Atmel, ATA5773-DK1 Datasheet - Page 41

• Manufacturer Part Number: ATA5773-DK1
• Description: BOARD XMITTER FOR ATA5773 315MHZ
• Manufacturer: Atmel
• Type: Transmitterr

Specifications of ATA5773-DK1

• Frequency: 315MHz
• Maximum Frequency: 315 MHz
• Supply Voltage (max): 4 V
• Supply Voltage (min): 2 V
• Supply Current: 9 mA
• Product: RF Development Tools
• For Use With/related Products: ATA5773
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.10
4.10.1
4.10.2
9137E–RKE–12/10
Power Management and Sleep Modes
Sleep Modes
Idle Mode
Sleep modes enable the application to shut down unused modules in the MCU, thereby saving
power. The Atmel
consumption to the application’s requirements.
Figure 4-10 on page 32
distribution. The figure is helpful in selecting an appropriate sleep mode.
different sleep modes and their wake up sources
Table 4-13.
Note:
To enter any of the three sleep modes, the SE bit in MCUCR must be written to logic one and
a SLEEP instruction must be executed. The SM1..0 bits in the MCUCR Register select which
sleep mode (Idle, ADC Noise Reduction, Standby or Power-down) will be activated by the
SLEEP instruction. See
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU
is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and
resumes execution from the instruction following SLEEP. The contents of the Register File
and SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep
mode, the MCU wakes up and executes from the Reset Vector.
When the SM1..0 bits are written to 00, the SLEEP instruction makes the MCU enter Idle
mode, stopping the CPU but allowing Analog Comparator, ADC, Timer/Counter, Watchdog,
and the interrupt system to continue operating. This sleep mode basically halts clk
FLASH
Idle mode enables the MCU to wake up from external triggered interrupts as well as internal
ones like the Timer Overflow. If wake-up from the Analog Comparator interrupt is not required,
the Analog Comparator can be powered down by setting the ACD bit in the Analog Compara-
tor Control and Status Register – ACSR. This will reduce power consumption in Idle mode. If
the ADC is enabled, a conversion starts automatically when this mode is entered.
Sleep Mode
Idle
ADC Noise
Reduction
Power-down
Stand-by
, while allowing the other clocks to run.
1. For INT0, only level interrupt.
2. Only recommended with external crystal or resonator selected as clock source
(2)
Active Clock Domains and Wake-up Sources in the Different Sleep Modes
®
Active Clock Domains
AVR
presents the different clock systems in the Atmel ATtiny44V, and their
Table 4-14 on page 44
®
provides various sleep modes allowing the user to tailor the power
X
X
X
Oscillators
for a summary.
X
X
Atmel ATA5771/73/74
X
X
X
X
(1)
(1)
Wake-up Sources
X
X
X
(1)
Table 4-13
X
X
CPU
shows the
X
and clk-
X
X
X
41