AD9861BCPZ-50 Analog Devices Inc, AD9861BCPZ-50 Datasheet - Page 6

• Manufacturer Part Number: AD9861BCPZ-50
• Description: IC FRONT-END MIXED SGNL 64-LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9861BCPZ-50

• Rf Type: WLL, WLAN
• Features: 10-bit ADC(s), 10-bit DAC(s)
• Package / Case: 64-LFCSP
• Supply Voltage Range: 2.7V To 3.6V
• Logic Case Style: LFCSP
• No. Of Pins: 64
• Operating Temperature Range: -40°C To +85°C
• Msl: MSL 3 - 168 Hours
• Termination Type: SMD
• Interface: SPI
• No. Of Channels: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD9861
TIMING SPECIFICATIONS
Table 5. AD9861-50 and AD9861-80
Parameter
INPUT CLOCK
TxPATH DATA
RxPATH DATA
Table 6. Explanation of Test Levels
Level
I
II
III
IV
V
VI
CLKIN Clock Rate (PLL Bypassed)
PLL Input Frequency
PLL Ouput Frequency
Setup Time (HD20 Mode, Time Required Before Data Latching
Edge)
Hold Time (HD20 Mode, Time Required After Data Latching
Edge)
Latency 1× Interpolation (data in until peak output response)
Latency 2× Interpolation (data in until peak output response)
Latency 4× Interpolation (data in until peak output response)
Output Delay (HD20 Mode, t
Latency
Description
100% production tested.
100% production tested at 25°C and guaranteed by design and characterization at specified temperatures.
Sample tested only.
Parameter is guaranteed by design and characterization testing.
Parameter is a typical value only.
100% production tested at 25°C and guaranteed by design and characterization for industrial temperature range.
OD
)
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Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Test Level
IV
IV
IV
V
V
V
V
V
V
V
Min
1
16
32
Typ
5
–1.5
7
35
83
–1.5
5
Max
200
200
350
Unit
MHz
MHz
MHz
ns (see Clock
Distribution Block
section)
ns (see Clock
Distribution Block
section)
DAC Clock Cycles
DAC Clock Cycles
DAC Clock Cycles
ns (see Clock
Distribution Block
section)
ADC Clock Cycles