T4260-ILSH Atmel, T4260-ILSH Datasheet
T4260-ILSH
Specifications of T4260-ILSH
Related parts for T4260-ILSH
T4260-ILSH Summary of contents
Page 1
... High S/N Ratio • 3-wire Bus (Enable, Clock and Data; 3V and 5V Microcontrollers-compatible) 1. Description The T4260 is an advanced AM/FM receiver with integrated fast PLL as a single-chip ® solution based on Atmel ’s high-performance BICMOS II technology. The low-imped- ance driver at the IF output is designed for the A digital IF. The fast tuning concept realized in this part is based on patents held by Atmel and allows lock times less than 1 ms for a jump over the FM band with a step width of 12 ...
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... MXAMOB MXFMIA 5 MXFMIB 6 GNDRF 7 MXAMIB 8 MXAMIA 42 RFAGCA1 33 RFAGCFM AGC 12 RFAGCA2 FM AM AMAGCO 9 FMAGCO 3 VCO OSCBUF OSCE OSCB T4260 2 MXAMOA IFINAM IFREF ININFM DIV N DIV PD R DIV 27 REFFREQ OSCGND IFAGCFM IFAGCA2 IFOUTA IFOUTB IFAGCA1 RF/IF SUPPLY AGC PLL SUPPLY BUS SW-AMLF 16 18 ...
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... FM mixer input A FM mixer input B RF ground AM mixer input B AM mixer input A AM AGC current AM IF-AGC filter 2 Switch 2/AM AGC voltage RF AM-AGC filter 2 Switching output 1 VCO reference voltage PLL supply voltage FM loop filter AM loop filter Tuning voltage Oscillator ground Oscillator emitter T4260 3 ...
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... MXFMOB 3. Functional Description The T4260 implements an AM up-conversion reception path from the RF input signal to the IF output signal. A VCO and an LO prescaler for AM are integrated to generate the LO frequency to the AM mixer. The FM reception path generates the same LO frequency from the RF input sig- nal by a down-conversion to the IF output. The IF A/D output is designed for digital signal processing ...
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... Value 52 Min. Typ. Max. 8 8.5 10 – 175 Min. Typ. Max 8 110 S 3 16383 3 262143 100 120 150 10000 120 2850 10000 T4260 Unit V W °C °C °C Unit K/W Unit V °C MHz Unit Type rms kHz kHz 5 ...
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... Noise figure Conversion 7.6 transconductance *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note: 1. Minimum and maximum limits are characterized for entire temperature range (–40°C to +85°C) but are tested at +25°C T4260 +8.5V +25°C ST SPLL amb ...
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... T4260 Unit Type* MHz B dBµ ( MHz A MHz (1) dBµV A (1) dBµV A (1) dBµV A (1) dBµV A (1) dBµV A (1) dBµV A (1) dBµV A (1) dBµV A (1) dBµV A (1) dBµ ...
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... AGC time constant 12.3 (external capacity 100 nF) *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note: 1. Minimum and maximum limits are characterized for entire temperature range (–40°C to +85°C) but are tested at +25°C T4260 +8.5V +25°C ST SPLL ...
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... SWOL I 10 OHL 8.5 100 160 200 SWOL I 10 OHL 6 V 2.7 5.3 BUS V -0.3 +0.8 BUS 1.0 t 250 H t 250 L t 400 R t 100 F t 100 S t 250 HEN t 0 HDA T4260 Unit Type ...
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... Bus Description The register settings of the T4260 are programmed by a 3-wire bus protocol. The bus protocol consists of separate commands. A defined number of bits is transmitted sequentially during each command. One command is used to program all bits of one register. The different registers available (see ...
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... Figure 8-2. 3-wire Bus Timing Diagram t F Enable Data Clock 4528N–AUDR–11/09 t HDA T4260 High V t Low HEN High V Low High V Low 11 ...
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... Note: 1. Value has A16_11 MSB BYTE 1 DAC2-Gain A16_10 MSB BYTE 1 DAC2-Offset A16_01 MSB BYTE 1 DAC1-Gain T4260 12 LSB MSB BYTE 2 R-Divider 139 138 137 136 135 LSB MSB BYTE 2 N2-Divider 102 117 116 115 114 113 LSB MSB BYTE 2 N1-Divider LSB MSB BYTE 2 ADDR ...
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... AM/FM IF-AGC RF-AGC 1/0 1 A8_01 MSB BYTE 1 ADDR. IF-IN VCO IF-Gain AM/FM HI/ A8_00 MSB BYTE 1 PLL PD TE/ ADDR. N2/N1 ON/ PD OFF ( 1/0 1 Note: 1. Value has 4528N–AUDR–11/09 LSB MSB ADDR LSB x HCDEL ( LSB LSB LSB IF-AGC BYTE 2 LSB SHIFT ( 1 T4260 13 ...
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... PD Test A special test mode for PD is implemented for final production test only. This mode is activated by setting bit This mode is not intended to be used by customer application. For normal operation bit 3 has to be set to 0. Table 10-3. T4260 14 IF-AGC Threshold IF-AGC B2 109 dBµV 0 111 dBµ ...
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... The VCO HI/LO function is controlled by means of bit 10. Table 10-7. 4528N–AUDR–11/09 N-Divider N2/N1 N1-divider active N2-divider active IF Gain IF Gain ... ... IF-IN Operating Mode IF-IN AM/FM IF-IN FM IF-IN AM VCO Operating Mode VCO HI/LO VCO high current VCO low current Table ... ... Table B11 0 1 B10 0 1 T4260 10- ... 0 1 10-6. 15 ...
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... reception mode, bit 145 has to be set to the corresponding mode. The buffer ampli- fier input can be connected to pin 16 (with the external FM loop filter) by bit 145 = 0 and to pin 17 (with the external AM loopfilter) by bit 145 = 1. The AM/FM function for the tuner part is controlled by bit 17 as given in Table 10-9. T4260 16 RF-AGC RF-AGC FM 91 dBµV 92 dBµ ...
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... Otherwise, the delay time can be selected as described in 10-12. Table 10-12. Delay Time of HCDEL Register 4528N–AUDR–11/09 PLL ON/OFF PLL OFF PLL ON HCDEL 1/2 Select Mode HCDEL 1 HCDEL 2 High-current Charge Pump OFF Delay time 5 ns Delay time 10 ns Delay time HCDEL (B18 B21/B23 B20/B22 T4260 Table 17 ...
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... Table 10-13. Manual and Lock Detect Shift Mode 10.11 SW1 (Pin 13) The switching output SW1 (pin 13) is controlled by bit 46 as given in Table 10-14. Switching Output Note: Figure 10-1. Internal Components at SW1 T4260 kHz instead of f PDF 2-bit Shift Dividers 2-bit shift ...
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... This mode is not intended to be used by customer application. For normal operation bit 123 has to be set to 0. Table 10-16. Test Mode 4528N–AUDR–11/09 SW2/AGC AGC function High Low In AGC mode, the output voltage is 6V down to 1V. SWO/AGC Test Mode ON OFF T4260 Table 10-15. B48 B47 ...
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... In the FM mixer stage, the FM reception frequency is down-converted to the IF frequency. The VCO frequency is used as LO frequency for the mixer. 10.16 PLL Loop Filter The PLL loop filter selection for AM and FM mode can be controlled by bit 145 as given in 10-18. Table 10-18. Loop Filter Operating Mode T4260 20 Divider AM Prescaler Divide by 2 Divide by 3 Divide by 4 ...
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... In fractional and direct shift mode the spurious suppression is able by SW wire and SW impulse. Table 10-20. Spurious Suppression by SW Wire Table 10-21. Spurious Suppression by Correction Current Charge Pump 4528N–AUDR–11/09 Fractional ON OFF SW Wire OFF ON SW Impulse OFF ON T4260 B144 0 1 B60 0 1 B61 ...
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... If this is not done, the IC operates in standard mode (bit 65 = 1). The oscillator, oscillator buffer and the AMLF are controlled by the bits 65 and 64 as given in Table 10-24 on page Table 10-24. Oscillator Operating Modes Oscillator T4260 22 High-current Charge Pump Low Current Charge Pump 50 µ ...
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... V(TUNE V(TUNE Offset = 64 (intermediate position) Figure 10-3. The gain is in the range DAC1, 2 +/- Offset V(TUNE given in Table B42 B41 B40 B39 B38 B70 B69 B68 B67 B66 ... ... ... ... ... ... ... ... ... ... T4260 V(TUNE and the 10-25. Decimal Gain Decimal Gain ... 58 ... 253 254 255 23 ...
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... OP input voltage does not exceed 0.5V. VTUNE ( 1V) < 10V + 3V (condition not allowed) This means when having a gain factor of 2 and an offset value of 1V, the tuning voltage should not exceed 6V. T4260 ...
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... VTUNE, AMLF and FMLF (Pins 16-18) VTUNE is the loop amplifier output of the PLL. The bipolar output stage is a rail-to-rail amplifier. Figure 11-1. Internal Components at VTUNE, AMLF and FMLF 4528N–AUDR–11/ DAC offset)/DAC gain factor S DAC1 VTUNE AMLF/FMLF T4260 25 ...
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... Figure 11-3. Block Diagram of the PLL Core 14 - BIT LATCH R - DIV. SHIFT 2 BIT DIVIDER ref N/N+1 DIVIDER SHIFT 2 BIT MUX LATCH N - DIV BIT T4260 26 Section 8. “3-wire Bus Description” on page EN DATA CLK SWITCH HCDEL 1 HCDEL 2 DELAYTIME high cur. CP PHASE CHARGE DETECTOR PREAMP ...
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... In direct shift mode, the R- and the N-divider are shifted by 2 bits to PDF 10.7 MHz + 103.2125 MHz = 113.9125 MHz VCO IF rec 113.9125 MHz/9113 = 150 kHz/12 = 12.5 kHz PDF VCO ref T4260 low frequency PDF = 12.5 kHz. PDF = 12.5 kHz and f = 10.7 MHz), an PDF IF ) ref 27 ...
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... MHz to 124 MHz VCO f = 10.7 MHz rec VCO prescaler VCO The following formula can also be useful by AM frequencies higher than 20 MHz prescaler VCO T4260 28 lists the AM prescaler (divider) settings and the reception frequencies. – rec IF (f – rec then 113.9 MHz (instead of 113.9125 MHz in ...
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... By using two ICs, for example possible to operate the AMLF (pin 17) of the second IC either with the tuning voltage (VTUNE [pin 18]), the DAC 1 voltage [pin 1] or the DAC 2 voltage [pin 2] from the first T4260. For voltage reduction at the AMLF [pin 17], a voltage factor ratio of 100/ required ...
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... SWAMLF voltage = (10V + 3V – 1V)/( also possible to reduce the gain or offset instead (or along with) the SWAMLF voltage. T4260 30 T4260 VTUNE or DAC ([ ]/R ) DAC gain factor + DAC offset < )/ – DAC offset)/(DAC gain factor S Gain AMLF T4260 24 7.25) 7.25) = 0.83V 4528N–AUDR–11/09 ...
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... VRVCO IFAGCFM 100n 15 VSPLL IFOUTA 16 FMLF IFOUTB 17 AMLF GNDPLL 18 VTUNE REFFREQ 19 OSCGND VRPLL 1n 20 OSCE DATA 22p 47p 21 OSCB CLK 22 OSCBUF EN 10n 10n Test Point 44 330 100n VST 100n 36 330 35 2k4 34 100n 33 100k 32 100k 31 30 100 10n 10n 25 BUS 24 23 T4260 31 ...
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... R VS_T 2R7 100n 10µ 100p DAC1 10n 16 DAC2 10n 68k F 3 68k R 9 470 R 10 10p 2µ 10n BFR93A Bu1 Ant T4260 180 C C KF2 1µ 100n 2k2 KF1 300 F1 6 300 220n 100n 47p 4µ7 100n 100n C 31 12p 100µ ...
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... Figure 11-6 “Application Circuit” on page 32 changed Put datasheet in a new template Number 6.4 in section 7 “Electrical Characteristics” on page 6 added Put datasheet in a new template Pb-free logo on page 1 deleted Table 10-8 “RF-AGC” on page 17 changed T4260 9.15 8.65 7.50 7.30 0.25 10 ...
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... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...