SI4322-A1-FT Silicon Laboratories Inc, SI4322-A1-FT Datasheet - Page 12

• Manufacturer Part Number: SI4322-A1-FT
• Description: IC RCVR FSK 915MHZ 3.8V 16-TSSOP
• Manufacturer: Silicon Laboratories Inc
• Type: FSK Receiverr

Specifications of SI4322-A1-FT

• Package / Case: 16-TSSOP
• Frequency: 868MHz, 915MHz
• Sensitivity: -104dBm
• Data Rate - Maximum: 256 kbps
• Modulation Or Protocol: FSK
• Applications: Remote Control, RKE, Security Systems
• Current - Receiving: 14mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Features: RSSI Equipped
• Voltage - Supply: 2.2 V ~ 3.8 V
• Operating Frequency: 915 MHz
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Current: 12 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Memory Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed
• Other names: 336-1628-5

Si4322
Digital operation: The data filter is a digital realization of an analog RC filter followed by a comparator with
hysteresis. In this mode, there is a clock recovery circuit (CR), which can provide synchronized clock to the data.
With this clock, the received data can fill the RX Data FIFO. The CR has three operation modes: fast, slow, and
automatic. In slow mode, its noise immunity is very high, but it has slower settling time and requires more accurate
data timing than in fast mode. In automatic mode the CR automatically changes between fast and slow modes. The
CR starts in fast mode, and then automatically switches to slow mode after locking.
Only the data filter and the clock recovery use the bit rate clock. Therefore, in analog mode, there is no need for
setting the correct bit rate.
4.5. Data Validity Blocks
4.5.1. RSSI
A digital RSSI output is provided to monitor the input signal level. It goes high if the received signal strength
exceeds a given preprogrammed level. An analog RSSI signal is also available. The RSSI settling time depends on
the filter capacitor used.
4.5.2. DQD
The Data Quality Detector monitors the I/Q output of the baseband amplifier chain by counting the consecutive
0
counter. If the counter result exceeds this parameter, then DQD output indicates good FSK signal quality. Using
this method, it is possible to "forecast” the probability of BER degradation. In cases when the deviation is close to
the bit rate, there should be four transitions during a single one-bit period in the I/Q signals. As the bit rate
decreases in comparison to the deviation, more and more transitions will happen during a bit period.
4.5.3. AFC
By using an integrated Automatic Frequency Control (AFC) feature, the receiver can synchronize its local oscillator
to the received signal, allowing the use of the following:



4.6. Crystal Oscillator and Microcontroller Clock Output
The chip has a single-pin crystal oscillator circuit, which provides a 10 MHz reference signal for the PLL. To reduce
external parts and simplify design, the crystal load capacitor is internal and programmable. Guidelines for selecting
the appropriate crystal can be found later in this data sheet. The receiver can supply the clock signal for the
microcontroller, so accurate timing is possible without the need for a second crystal. In normal operation, it is
divided from the reference 10 MHz. During sleep mode, a low frequency (typical 32 kHz) output clock signal can be
switched on, which is provided by a low-power RC oscillator.
When the microcontroller turns the crystal oscillator off by clearing the appropriate bit using the
Setting Command" on page 16
(“clock tail”) for the microcontroller to let it go to idle or sleep mode.
12

1 and 1
inexpensive, low accuracy crystals
narrower receiver bandwidth (i.e., increased sensitivity)
higher data rate

0 transitions during a single bit period. The programmable DQD parameter defines a threshold for this
Figure 2. Typical Analog ARSSI Voltage vs. RF Input Power
, the chip provides a programmable number (default is 512) of further clock pulses
1150
450
-100
Input Power [dBm]
Rev. 1.2
-65
"5.3. Configuration