SI4322-A1-FT Silicon Laboratories Inc, SI4322-A1-FT Datasheet - Page 23

• Manufacturer Part Number: SI4322-A1-FT
• Description: IC RCVR FSK 915MHZ 3.8V 16-TSSOP
• Manufacturer: Silicon Laboratories Inc
• Type: FSK Receiverr

Specifications of SI4322-A1-FT

• Package / Case: 16-TSSOP
• Frequency: 868MHz, 915MHz
• Sensitivity: -104dBm
• Data Rate - Maximum: 256 kbps
• Modulation Or Protocol: FSK
• Applications: Remote Control, RKE, Security Systems
• Current - Receiving: 14mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Features: RSSI Equipped
• Voltage - Supply: 2.2 V ~ 3.8 V
• Operating Frequency: 915 MHz
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Current: 12 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Memory Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed
• Other names: 336-1628-5

2. (a1=0, a0=1) The circuit measures the frequency offset only once after power up. This way, extended TX-RX
3. (a1=1, a0=0) The frequency offset is calculated automatically and the center frequency is corrected when the
4. (a1=1, a0=1) It is similar mode 3, but suggested to use when a receiver operates with only one transmitter. After
5.12. Data Filter Command
Bit 7 <al>: Clock recovery (CR) auto lock control
Bit 6 <ml>: Clock recovery lock control
Bit 5 <dsfi>: Disables auto-sleep on FIFO interrupt if set to 1.
This mode helps to decrease the average current consumption of the receiver. In normal mode (auto-sleep is
disabled) the receiver remains active after receiving a given number of bits (set by the FIFO IT level, see the "5.14.
FIFO Settings Command" on page 25). If the auto-sleep is enabled the part goes to stand-by mode when FIFO
interrupt occurs – increasing this way the battery life. Use this mode when the transmitted data length is known and
set the FIFO IT level to this value.
Bit 4 <sf>: Selects the type of the data filter
Digital Filter: This is a digital realization of an analog RC filter followed by a comparator with hysteresis. The time
constant is automatically adjusted to the bit rate defined by the
Note: Bit rate cannot exceed 115 kbps in this mode.
distance can be achieved. In the final application, during the first receiving cycle, the circuit measures and
compensates for the frequency offset caused by the crystal tolerances. This method allows the use of lower
cost crystal in the application and provides protection against tracking an interferer.
VDI is high. The calculated value is dropped when the VDI goes low. To improve the efficiency of the AFC
calculation two methods are recommended:
In both cases (3a and 3b), when the VDI indicates poor receiving conditions (VDI goes low), the output register
is automatically cleared. Use this “drop offset” mode when the receiver communicates with more than one
transmitter.
a complete measuring cycle, the measured value is kept independently of the state of the VDI signal. When the
receiver is paired with only one transmitter, it is possible to use this “keep offset” mode. In this case, the DRSSI
limit should be selected carefully to minimize the range hysteresis.
Bit
a. The transmit package should start with a low effective baud rate pattern (i.e.: 00110011) because it is
b. The transmitter sends the first part of the packet with a step higher deviation than required during normal
15
easier to receive. The circuit automatically measures the frequency offset during this initial pattern and
changes the receiving frequency accordingly. The further part of the package will be received by the
corrected frequency settings.
operation to ease the receiving. After the frequency shift was corrected, the deviation can be reduced.
1
1: auto mode: the CR starts in fast mode and after locking it switches to slow mode. The ml bit (Bit 6)
has no effect.
0: manual mode: the clock recovery mode is set by Bit 6 <ml>
1: fast mode, fast attack and fast release (4 to 8-bit preamble (1010...) is recommended)
0: slow mode, slow attack and slow release (12 to 16-bit preamble is recommended)
Using the slow mode requires more accurate bit timing (see
14
1
13
0
12
0
11
0
10
1
9
0
sf
0
1
8
0
Analog RC filter
Rev. 1.2
al
7
Filter Type
Digital filter
ml
6
"5.13. Data Rate Command" on page 24
dsfi
5
sf
4
"5.13. Data Rate Command" on page 24
ewi
3
f2
2
f1
1
f0
0
Si4322
.
C462h
POR
).
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