SI4322-A1-FT Silicon Laboratories Inc, SI4322-A1-FT Datasheet - Page 29
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SI4322-A1-FT
Manufacturer Part Number
SI4322-A1-FT
Description
IC RCVR FSK 915MHZ 3.8V 16-TSSOP
Manufacturer
Silicon Laboratories Inc
Type
FSK Receiverr
Specifications of SI4322-A1-FT
Package / Case
16-TSSOP
Frequency
868MHz, 915MHz
Sensitivity
-104dBm
Data Rate - Maximum
256 kbps
Modulation Or Protocol
FSK
Applications
Remote Control, RKE, Security Systems
Current - Receiving
14mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Features
RSSI Equipped
Voltage - Supply
2.2 V ~ 3.8 V
Operating Frequency
915 MHz
Operating Supply Voltage
2.5 V, 3.3 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Current
12 mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Memory Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
Other names
336-1628-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SI4322-A1-FT
Manufacturer:
INTERSIL
Quantity:
747
7. FIFO Buffered Data Read
In this operating mode, incoming data are clocked into a 64-bit FIFO buffer. The receiver starts to fill up the FIFO
when the Valid Data Indicator (VDI) bit and/or the synchron word recognition circuit indicates potentially real
incoming data. This prevents the FIFO from being filled with noise and overloading the external microcontroller.
For further details see "5.5. Receiver Setting Command" on page 18 and "5.14. FIFO Settings Command" on page
25.
7.1. Polling Mode
The nFFS signal selects the buffer directly and its content could be clocked out through pin SDO by SCK. Set the
FIFO IT level to 1. In this case, as long as FFIT indicates received bits in the FIFO, the controller may continue to
take the bits away. When FFIT goes low, no more bits need to be taken. An SPI read command is also available.
7.2. Interrupt Controlled Mode
The user can define the FIFO level (the number of received bits) which will generate the nFFIT when exceeded.
The status bits report the changed FIFO status in this case.
7.3. FIFO Read Example with FFIT Polling
Note: During FIFO access f
of the clock signal is not 50% the shorter period of the clock pulse should be at least 2/f
SCK
cannot be higher than f
nSEL
SCK
SDI
nFFS *
SDO
FFIT
FIFO OUT
0
ref
FO+1
/4, where f
1
FIFO read out
Rev. 1.2
FO+2
2
FO+3
ref
3
NOTE:
*nFFS selects FIFO read mode
is the crystal oscillator frequency. When the duty-cycle
FO+4
4
ref
.
Si4322
29