ATA5811-PLHC Atmel, ATA5811-PLHC Datasheet - Page 42
![IC TXRX UHF ASK/FSK 1CH 48-QFN](/photos/7/34/73471/48-vqfn-6_543-5130_01-4_sml.jpg)
ATA5811-PLHC
Manufacturer Part Number
ATA5811-PLHC
Description
IC TXRX UHF ASK/FSK 1CH 48-QFN
Manufacturer
Atmel
Datasheet
1.ATA5811-PLHC.pdf
(92 pages)
Specifications of ATA5811-PLHC
Frequency
433MHz, 868MHz
Data Rate - Maximum
20kbps
Modulation Or Protocol
ASK, FSK
Applications
Access Control, AMR, RKE
Power - Output
5dBm
Sensitivity
-116dBm
Voltage - Supply
2.4 V ~ 3.6 V or 4.4 V ~ 6 V
Current - Receiving
10.5mA
Current - Transmitting
16mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Memory Size
-
Other names
ATA5811-PLHCTR
ATA5811-PLQ
ATA5811-PLQTR
ATA5811-PLQTR
ATA5811-PLQ
ATA5811-PLQTR
ATA5811-PLQTR
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42
ATA5811/ATA5812
If the transceiver is in any active mode (Idle, AUX, TX, RX, RX_Polling), an integrated debounce
logic is active. If there is an event on pin Tn a debounce counter is set to 0 (T = 0) and started.
The status is updated, an interrupt is issued and the debounce counter is stopped after reaching
the counter value T = 8195
An event on the same key input before reaching T = 8195
An event on an other key input before reaching T = 8195
debounce counter.
While the debounce counter is running, the bits VSOUT_EN and CLK_ON in control register 3
are set to 1.
The interrupt is deleted after reading the status register or executes the command Delete_IRQ.
If a pin Tn is not used, it can be left open because of an internal pull-up resistor (typically 50 k ).
Figure 9-3.
Timing Flow Pin Tn, Status Bit STn
Start debounce counter
Stop debounce counter
RX Polling Mode or
Event on Pin Tn ?
Event on Pin Tn ?
IDLE Mode or
AUX Mode or
TX Mode or
Tn = STn ?
RX Mode
T = 0
Y
Y
Y
T
DCLK
N
N
N
.
Stop debounce counter
T = 8195
Pin Tn = 0 ?
STn = 1
IRQ = 1
Y
Y
T ?
N
N
T
DCLK
Stop debounce counter
T
DCLK
stops the debounce counter.
STn = 0
IRQ = 1
resets and restarts the
4689F–RKE–08/06
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