SI4420-D1-FT Silicon Laboratories Inc, SI4420-D1-FT Datasheet - Page 4

• Manufacturer Part Number: SI4420-D1-FT
• Description: IC TXRX FSK 915MHZ 5.4V 16-TSSOP
• Manufacturer: Silicon Laboratories Inc

Specifications of SI4420-D1-FT

• Package / Case: 16-TSSOP
• Frequency: 315MHz, 433MHz, 868MHz, and 915MHz
• Data Rate - Maximum: 256kbps
• Modulation Or Protocol: FSK
• Power - Output: -21dbm
• Sensitivity: -109dBm
• Voltage - Supply: 2.2 V ~ 5.4 V
• Current - Receiving: 15mA
• Current - Transmitting: 26mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Number Of Receivers: 2
• Number Of Transmitters: 2
• Wireless Frequency: 315 MHz to 915 MHz
• Interface Type: SPI
• Output Power: 4 dBm to 8 dBm
• Operating Supply Voltage: 2.2 V to 5.4 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 25 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Applications: -
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1630-5

PACKAGE PIN DEFINITIONS
Pin type key: D=digital, A=analog, S=supply, I=input, O=output, IO=input/output
Note: The actual mode of the multipurpose pins (pin 6 and 7) is determined by the TX/RX data I/O settings of the transceiver.
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Name
SDI
SCK
nSEL
SDO
nIRQ
FSK
DATA
nFFS
DLCK
CFIL
FFIT
CLK
XTL
REF
nRES
VSS
RF2
RF1
VDD
ARSSI
nINT
VDI
Type
DI
DI
DI
DO
DO
DI
DO
DI
DO
AIO
DO
DO
AIO
AIO
DIO
S
AIO
AIO
S
AO
DI
DO
Function
Data input of the serial control interface
Clock input of the serial control interface
Chip select input of the serial control interface (active low)
Serial data output with bus hold (tri-state)
Interrupt request output (active low)
Transmit FSK data input
Received data output (FIFO not used)
FIFO select input (active low) In FIFO mode, when bit ef is set in Configuration Setting Command
Received data clock output (Digital filter used, FIFO not used)
External data filter capacitor connection (Analog filter used)
FIFO interrupt (active high) Number of the bits in the RX FIFO that reach the preprogrammed limit
In FIFO mode, when bit ef is set in Configuration Setting Command
Microcontroller clock output
Crystal connection (the other terminal of crystal to VSS) or external reference input
External reference input. Use 33 pF series coupling capacitor
Open drain reset output with internal pull-up and input buffer (active low)
Ground reference voltage
RF differential signal input/output
RF differential signal input/output
Positive supply voltage
Analog RSSI output
Interrupt input (active low)
Valid data indicator output
Si4420
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