ATA5429-PLSW Atmel, ATA5429-PLSW Datasheet - Page 51
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ATA5429-PLSW
Manufacturer Part Number
ATA5429-PLSW
Description
IC TXRX ASK/FSK 915MHZ 48QFN
Manufacturer
Atmel
Specifications of ATA5429-PLSW
Frequency
915MHz
Data Rate - Maximum
20kbps
Modulation Or Protocol
ASK, FSK
Applications
Alarm, ISM, Telemetry
Power - Output
5dBm
Sensitivity
-112.5dBm
Voltage - Supply
2.4 V ~ 3.6 V or 4.4 V ~ 6.6 V
Current - Receiving
10.5mA
Current - Transmitting
10mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Operating Temperature Classification
Industrial
Product Depth (mm)
7mm
Product Height (mm)
0.9mm
Product Length (mm)
7mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Memory Size
-
Lead Free Status / Rohs Status
Compliant
8.8
Figure 8-7.
4841D–WIRE–10/07
4-wire Serial Interface
SDO_TMDO
SDI_TMDI
Serial Timing
SCK
CS
T
SCK_setup1
X
X can be either V
Table 8-1.
The 4-wire serial interface consists of the Chip Select (CS), the Serial Clock (SCK), the Serial
Data Input (SDI_TMDI) and the Serial Data Output (SDO_TMDO). Data is transmitted/received
bit by bit in synchronization with the serial clock.
Note:
When CS is low and the transparent mode is inactive (T_MODE = 0), SDO_TMDO is in a high
impedance state. When CS is low and the transparent mode is active (T_MODE = 1), the RX
data stream is available on pin SDO_TMDO.
Command
Read TX/RX data buffer
Write TX/RX data buffer
Read control/status register
Write control register
OFF command
Delete IRQ
Not used
Not used
X
T
T
T
Setup
CS_setup
Out_enable
If the output level on pin N_RESET is low, no data communication with the microcontroller is
possible.
iL
Command Structure
MSB
or V
T
Hold
MSB
iH
ATA5423/ATA5425/ATA5428/ATA5429
T
Cycle
T
X
Out_delay
MSB
Bit 7
0
0
0
0
1
1
1
1
MSB-1
Bit 6
0
0
1
1
0
0
1
1
MSB-1
Bit 5
0
1
0
1
0
1
0
1
X
Bit 4
A4
A4
X
X
X
X
x
x
LSB
T
SCK_setup2
Bit 3
A3
A3
X
X
X
X
x
x
X
T
T
Bit 2
CS_disable
Out_disable
A2
A2
X
X
X
X
x
x
T
X
SCK_hold
Bit 1
A1
A1
X
X
X
X
x
x
Bit 0
LSB
A0
A0
X
X
X
X
x
x
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