ATMEGA2561R231-MU Atmel, ATMEGA2561R231-MU Datasheet - Page 27

• Manufacturer Part Number: ATMEGA2561R231-MU
• Description: BUNDLE ATMEGA2561/RF231 QFN
• Manufacturer: Atmel

Specifications of ATMEGA2561R231-MU

• Frequency: 2.4GHz
• Modulation Or Protocol: 802.15.4 Zigbee, 6LoWPAN, RF4CE, SP100, WirelessHART™, ISM
• Data Interface: PCB, Surface Mount
• Memory Size: 256kB Flash, 4kB EEPROM, 8kB RAM
• Antenna Connector: PCB, Surface Mount
• Package / Case: 64-QFN, 32-QFN
• Processor Series: ATMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 8 KB
• Development Tools By Supplier: ATAVRRZ541, ATAVRRAVEN, ATAVRRZUSBSTICK, ATAVRISP2, ATAVRRZ201
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -
• Power - Output: -
• Operating Temperature: -
• Applications: -
• Sensitivity: -
• Data Rate - Maximum: -
• Current - Transmitting: -
• Current - Receiving: -
• Lead Free Status / Rohs Status: Details

7.4
7.4.1
2549M–AVR–09/10
I/O Memory
General Purpose I/O Registers
The I/O space definition of the ATmega640/1280/1281/2560/2561 is shown in
mary” on page
All ATmega640/1280/1281/2560/2561 I/Os and peripherals are placed in the I/O space. All I/O
locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data
between the 32 general purpose working registers and the I/O space. I/O Registers within the
address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In
these registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
Refer to the instruction set section for more details. When using the I/O specific commands IN
and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data
space using LD and ST instructions, 0x20 must be added to these addresses. The
ATmega640/1280/1281/2560/2561 is a complex microcontroller with more peripheral units than
can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For
the Extended I/O space from 0x60 - 0x1FF in SRAM, only the ST/STS/STD and LD/LDS/LDD
instructions can be used.
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most
other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore
be used on registers containing such Status Flags. The CBI and SBI instructions work with reg-
isters 0x00 to 0x1F only.
The I/O and peripherals control registers are explained in later sections.
The ATmega640/1280/1281/2560/2561 contains three General Purpose I/O Registers. These
registers can be used for storing any information, and they are particularly useful for storing
global variables and Status Flags. General Purpose I/O Registers within the address range 0x00
- 0x1F are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions. See
Description” on page
410.
35.
ATmega640/1280/1281/2560/2561
“Register Sum-
“Register
27