ATZB-24-A2 Atmel, ATZB-24-A2 Datasheet - Page 36

KIT MOD 802.15.4/ZIGB 2.4GHZ ANT

ATZB-24-A2

Manufacturer Part Number
ATZB-24-A2
Description
KIT MOD 802.15.4/ZIGB 2.4GHZ ANT
Manufacturer
Atmel
Datasheets

Specifications of ATZB-24-A2

Frequency
2.4GHz
Data Rate - Maximum
250kbps
Modulation Or Protocol
802.15.4 Zigbee
Applications
Home/Building Automation, Industrial Control and Monitoring
Power - Output
3dBm
Sensitivity
-101dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
19mA
Current - Transmitting
18mA
Data Interface
PCB, Surface Mount
Memory Size
128kBytes Flash, 8kBytes RAM, 4kBytes EEPROM
Antenna Connector
On-Board, Chip
Operating Temperature
-40°C ~ 85°C
Package / Case
Module
Tool Type
Wireless Development Kit
Core Architecture
AVR
Cpu Core
AVR 8
Data Bus Width
8 bit
Description/function
ZigBit 2.4 GHz Dual Chip Antenna
Wireless Frequency
2.4 GHz
Interface Type
UART, I2C, SPI
Operating Voltage
1.8 V to 3.6 V
Output Power
3 dBm
Antenna
Chip Antenna
Operating Temperature Range
- 40 C to + 85 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATZB-24-A2
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
ATZB-24-A2R
Manufacturer:
CIRRUS
Quantity:
201
20. TWI - Two-Wire Interface
20.1
20.2
8069Q–AVR–12/10
Features
Overview
The Two-Wire Interface (TWI) is a bi-directional wired-AND bus with only two lines, the clock
(SCL) line and the data (SDA) line. The protocol makes it possible to interconnect up to 128 indi-
vidually addressable devices. Since it is a multi-master bus, one or more devices capable of
taking control of the bus can be connected.
The only external hardware needed to implement the bus is a single pull-up resistor for each of
the TWI bus lines. Mechanisms for resolving bus contention are inherent in the TWI protocol.
PORTC and PORTE each has one TWI. Notation of these peripherals are TWIC and TWIE,
respectively.
Two Identical TWI peripherals
Simple yet Powerful and Flexible Communication Interface
Both Master and Slave Operation Supported
Device can Operate as Transmitter or Receiver
7-bit Address Space Allows up to 128 Different Slave Addresses
Multi-master Arbitration Support
Up to 400 kHz Data Transfer Speed
Slew-rate Limited Output Drivers
Noise Suppression Circuitry Rejects Spikes on Bus Lines
Fully Programmable Slave Address with General Call Support
Address Recognition Causes Wake-up when in Sleep Mode
I
2
C and System Management Bus (SMBus) compatible
XMEGA A4
36

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