SI4200-GM Silicon Laboratories Inc, SI4200-GM Datasheet - Page 21

• Manufacturer Part Number: SI4200-GM
• Description: IC TXRX TRI-BAND 32MLP
• Manufacturer: Silicon Laboratories Inc

Specifications of SI4200-GM

• Frequency: 850MHz, 900MHz, 1.8GHz
• Modulation Or Protocol: GSM
• Applications: Cellular, GSM Cellular Radio
• Voltage - Supply: 2.7 V ~ 3.3 V
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -
• Operating Temperature: -
• Sensitivity: -
• Memory Size: -
• Data Rate - Maximum: -
• Current - Transmitting: -
• Current - Receiving: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Frequency Synthesizer
The Si4134T dual frequency synthesizer is a monolithic
CMOS integrated circuit that performs IF and RF
synthesis. An integrated digitally-controlled crystal
oscillator (DCXO) is provided to generate the reference
clock. The DCXO allows the use of a standard crystal
resonator, avoiding the need for a crystal oscillator
module.
Two complete PLLs are integrated including VCOs,
varactors, resonators, loop filters, reference and VCO
dividers, and phase detectors. Differential outputs for
the IF and RF PLLs are provided for direct connection to
the Si4200 transceiver IC. The RF PLL uses two
multiplexed VCOs. The RF1 VCO is used for receive
mode, and the RF2 VCO is used for transmit mode. The
IF PLL is used only during transmit mode and uses a
single VCO.
The IF and RF output frequencies are set by
programming the N-Divider registers, N
N
or RF2 automatically selects the proper VCO. The
output frequency of each PLL is as follows:
A programmable divider in the input stage allows either
a 13 or 26 MHz reference frequency depending on the
choice of crystal. When configured for 26 MHz
operation using a TCXO, the DIV2 bit in Register 31h
IF
. Programming the N-Divider register for either RF1
XDRVEN
XTALEN
XTAL1
XTAL2
SCLK
XDRV
XAFC
SDO
PDN
SEN
SDI
CDAC[5:0]
DCXO
Control
Power
Serial
f
I/O
OUT
Figure 14. Si4134T Frequency Synthesizer Block Diagram
=
N f
SDOSEL[3:0]
PDIB
PDRB
÷1,2
DIV2
×
φ
÷130
RFUP
÷65,
RF1
, N
RF2
Tune
Tune
, and
DET
Self
Self
DET
φ
φ
Rev. 1.2
should be set appropriately. The RF PLL phase detector
update rate (f
in Register 31h to either f
Receive mode should use f
and PCS 1900 bands, and f
and E-GSM 900 bands. For transmit modes, the RF2
and IF PLL phase detector update rates should always
be configured for f
RF PLL
IF PLL
IFLA
RFLC
φ
) can be programmed with the RFUP bit
IFLB
φ
= 200 kHz.
N
N
RFLD
N
RF1
RF2
IF
[15:0]
[15:0]
÷N
÷N
[15:0]
RF1
RF2
φ
φ
= 100 kHz or f
= 200 kHz in the GSM 850
φ
= 100 kHz in DCS 1800
Si4134T
Aero+
φ
RFLOP
RFLON
IFLOP
IFLON
= 200 kHz.
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