SI4205-BM Silicon Laboratories Inc, SI4205-BM Datasheet - Page 20

• Manufacturer Part Number: SI4205-BM
• Description: IC TXRX TRI-BAND 32LGA
• Manufacturer: Silicon Laboratories Inc

Specifications of SI4205-BM

• Frequency: 850MHz, 900MHz, 1.8GHz, 1.9GHz
• Modulation Or Protocol: GSM
• Applications: Cellular, GSM Cellular Radio
• Voltage - Supply: 2.7 V ~ 3.3 V
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Package / Case: 32-LGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -
• Operating Temperature: -
• Sensitivity: -
• Memory Size: -
• Data Rate - Maximum: -
• Current - Transmitting: -
• Current - Receiving: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant

Aero I
Serial Interface
A three-wire serial interface is provided to allow an
external system controller to write the control registers
for dividers, receive path gain, powerdown settings, and
other controls. The serial control word is 24 bits in
length, comprised of an 18-bit data field and a 6-bit
address field as shown in Figure 12.
All registers must be written when the PDN pin is
asserted (low), except for register 22h. All serial
interface pins should be held at a constant level during
receive and transmit bursts to minimize spurious
emissions. This includes stopping the SCLK clock. A
timing diagram for the serial interface is shown in
Figure 3 on page 7.
When the serial interface is enabled (i.e., when SEN is
low), data and address bits on the SDI pin are clocked
into an internal shift register on the rising edge of SCLK.
Data in the shift register is then transferred on the rising
edge of SEN into the internal data register addressed in
the address field. The internal shift register ignores any
leading bits before the 24 required bits. The serial
interface is disabled when SEN is high.
Optionally, registers can be read as illustrated in
Figure 4 on page 7. The serial output data appears on
the SDO pin after writing the revision register with the
address to be read. Writing to any of the registers
causes the function of SDO to revert to its previously
programmed function.
20
17
D
16
D
15
D
14
D
Figure 12. Serial Interface Format
13
D
12
D
11
D
10
D
Data Field
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
5
A
4
Address
A
3
Field
A
2
clocked in
A
1
Last bit
A
0
Rev. 1.0
XOUT Buffer
The Aero I transceiver contains a reference clock buffer
to drive the baseband input. The clock signal from the
VC-TCXO is capacitively coupled to the XIN pin. The
clock signal is not divided with the XSEL control.
The XOUT buffer is a CMOS driver stage with
approximately 250 Ω of series resistance. This buffer is
enabled when the XEN hardware control (pin 26 on the
Si4205) is set high, independent of the PDN control pin.
To achieve complete powerdown during sleep, the XEN
pin must be set low, the XBUF bit in Register 12 must
be set to zero, and the XPD1 bit in Register 11 must be
set to one. During normal operation, these bits should
be set to their default values.