SI4030-A0-FM Silicon Laboratories Inc, SI4030-A0-FM Datasheet - Page 32

• Manufacturer Part Number: SI4030-A0-FM
• Description: IC TX ISM 930MHZ 3.6V 20-QFN
• Manufacturer: Silicon Laboratories Inc
• Type: ISM Transmitterr

Specifications of SI4030-A0-FM

• Package / Case: 20-QFN
• Frequency: 240MHz ~ 930MHz
• Modulation Or Protocol: FSK, GFSK, OOK
• Data Rate - Maximum: 128kbps
• Power - Output: 20dBm (100mW)
• Current - Transmitting: 28mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 1.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Operating Frequency: 240 MHz to 960 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Supply Current: 100 nA
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.8 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Applications: -
• Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 336-1624-5

Si4330-B1
6. Data Handling and Packet Handler
The internal modem is designed to operate with a packet including a 10101... preamble structure. To configure the
modem to operate with packet formats without a preamble or other legacy packet structures contact customer
support.
6.1. RX FIFO
A 64 byte FIFO is integrated into the chip for RX, as shown in Figure 11. "Register 7Fh. FIFO Access" is used to
access the FIFO. A burst read, as described in "3.1. Serial Peripheral Interface (SPI)" on page 16, from address
7Fh will read data from the RX FIFO.
The RX FIFO has one programmable threshold called the FIFO Almost Full Threshold, rxafthr[5:0]. When the
incoming RX data crosses the Almost Full Threshold an interrupt will be generated to the microcontroller via the
nIRQ pin. The microcontroller will then need to read the data from the RX FIFO.
The RX FIFO may be cleared or reset with the ffclrrx bit in “Register 08h. Operating Mode and Function Control 2,”
on page 71. All interrupts may be enabled by setting the Interrupt Enabled bits in "Register 05h. Interrupt Enable 1"
and “Register 06h. Interrupt Enable 2,” on page 69. If the interrupts are not enabled the function will not generate
an interrupt on the nIRQ pin but the bits will still be read correctly in the Interrupt Status registers.
32
Add R/W Function/D
Add R/W Function/De
7E
08
R/W
R/W
escription
Operating &
scription
Control 2
RX FIFO
Function
Control
antdiv[2] antdiv[1] antdiv[0]
Reserved Reserved rxafthr[5] rxafthr[4] rxafthr[3] rxafthr[2] rxafthr[1] rxafthr[0]
D7
D7
D6
D6
Figure 10. FIFO Threshold
RX FIFO
D5
D5
Rev 1.0
rxmpk
D4
D4
RX FIFO Almost Full
Reserved
Threshold
D3
D3
enldm
D2
D2
ffclrrx
D1
D1
Reserved
D0
D0
POR Def.
POR
00h
Def.
37h