PIC16F1828-I/SO Microchip Technology, PIC16F1828-I/SO Datasheet - Page 288
![IC PIC MCU 8BIT 14KB FLSH 20SOIC](/photos/28/72/287224/20-soic_sot163-1_sml.jpg)
PIC16F1828-I/SO
Manufacturer Part Number
PIC16F1828-I/SO
Description
IC PIC MCU 8BIT 14KB FLSH 20SOIC
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheets
1.PIC16F722-ISS.pdf
(8 pages)
2.PIC16F1826-IP.pdf
(40 pages)
3.PIC16F1824-ISL.pdf
(2 pages)
4.PIC16F1824-ISL.pdf
(419 pages)
5.PIC16F1824-ISL.pdf
(10 pages)
Specifications of PIC16F1828-I/SO
Core Size
8-Bit
Program Memory Size
7KB (4K x 14)
Core Processor
PIC
Speed
32MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (0.300", 7.50mm Width)
Controller Family/series
PIC16F
No. Of I/o's
18
Eeprom Memory Size
256Byte
Ram Memory Size
256Byte
Cpu Speed
32MHz
No. Of Timers
5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F1828-I/SO
Manufacturer:
TI/NSC
Quantity:
101
Part Number:
PIC16F1828-I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F722-ISS PDF datasheet
- PIC16F1826-IP PDF datasheet #2
- PIC16F1824-ISL PDF datasheet #3
- PIC16F1824-ISL PDF datasheet #4
- PIC16F1824-ISL PDF datasheet #5
- Current page: 288 of 419
- Download datasheet (4Mb)
PIC16(L)F1824/1828
25.6.13.2
During a Repeated Start condition, a bus collision
occurs if:
a)
b)
When the user releases SDA and the pin is allowed to
float high, the BRG is loaded with SSP1ADD and
counts down to zero. The SCL pin is then deasserted
and when sampled high, the SDA pin is sampled.
FIGURE 25-36:
FIGURE 25-37:
DS41419B-page 288
A low level is sampled on SDA when SCL goes
from low level to high level.
SCL goes low before SDA is asserted low,
indicating that another master is attempting to
transmit a data ‘1’.
SDA
SCL
BCL1IF
RSEN
S
SSP1IF
SDA
SCL
RSEN
BCL1IF
S
SSP1IF
Bus Collision During a Repeated
Start Condition
BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
SCL goes low before SDA,
set BCL1IF. Release SDA and SCL.
Preliminary
T
BRG
Sample SDA when SCL goes high.
If SDA = 0, set BCL1IF and release SDA and SCL.
If SDA is low, a bus collision has occurred (i.e., another
master is attempting to transmit a data ‘0’,
If SDA is sampled high, the BRG is reloaded and begins
counting. If SDA goes from high-to-low before the BRG
times out, no bus collision occurs because no two
masters can assert SDA at exactly the same time.
If SCL goes from high-to-low before the BRG times out
and SDA has not already been asserted, a bus collision
occurs. In this case, another master is attempting to
transmit a data ‘1’ during the Repeated Start condition,
see
If, at the end of the BRG time-out, both SCL and SDA
are still high, the SDA pin is driven low and the BRG is
reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated Start condition is
complete.
Figure
25-36.
T
Cleared by software
2010 Microchip Technology Inc.
BRG
Interrupt cleared
by software
‘0’
‘0’
‘0’
Figure
25-35).
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