PIC16F1828-I/SO Microchip Technology, PIC16F1828-I/SO Datasheet - Page 297
![IC PIC MCU 8BIT 14KB FLSH 20SOIC](/photos/28/72/287224/20-soic_sot163-1_sml.jpg)
PIC16F1828-I/SO
Manufacturer Part Number
PIC16F1828-I/SO
Description
IC PIC MCU 8BIT 14KB FLSH 20SOIC
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheets
1.PIC16F722-ISS.pdf
(8 pages)
2.PIC16F1826-IP.pdf
(40 pages)
3.PIC16F1824-ISL.pdf
(2 pages)
4.PIC16F1824-ISL.pdf
(419 pages)
5.PIC16F1824-ISL.pdf
(10 pages)
Specifications of PIC16F1828-I/SO
Core Size
8-Bit
Program Memory Size
7KB (4K x 14)
Core Processor
PIC
Speed
32MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (0.300", 7.50mm Width)
Controller Family/series
PIC16F
No. Of I/o's
18
Eeprom Memory Size
256Byte
Ram Memory Size
256Byte
Cpu Speed
32MHz
No. Of Timers
5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F1828-I/SO
Manufacturer:
TI/NSC
Quantity:
101
Part Number:
PIC16F1828-I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F722-ISS PDF datasheet
- PIC16F1826-IP PDF datasheet #2
- PIC16F1824-ISL PDF datasheet #3
- PIC16F1824-ISL PDF datasheet #4
- PIC16F1824-ISL PDF datasheet #5
- Current page: 297 of 419
- Download datasheet (4Mb)
REGISTER 25-5:
REGISTER 25-6:
2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7-1
bit 0
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
Master mode:
bit 7-0
10-Bit Slave mode — Most Significant Address byte:
bit 7-3
bit 2-1
bit 0
10-Bit Slave mode — Least Significant Address byte:
bit 7-0
7-Bit Slave mode:
bit 7-1
bit 0
R/W-0/0
R/W-1/1
ADD<7:0>: Baud Rate Clock Divider bits
SCL pin clock period = ((ADD<7:0> + 1) *4)/F
Not used: Unused for Most Significant Address byte. Bit state of this register is a “don’t care.” Bit
pattern sent by master is fixed by I
are compared by hardware and are not affected by the value in this register.
ADD<2:1>: Two Most Significant bits of 10-bit address
Not used: Unused in this mode. Bit state is a “don’t care.”
ADD<7:0>: Eight Least Significant bits of 10-bit address
ADD<7:1>: 7-bit address
Not used: Unused in this mode. Bit state is a “don’t care.”
MSK<7:1>: Mask bits
1 = The received address bit n is compared to SSP1ADD<n> to detect I
0 = The received address bit n is not used to detect I
MSK<0>: Mask bit for I
I
1 = The received address bit 0 is compared to SSP1ADD<0> to detect I
0 = The received address bit 0 is not used to detect I
2
C Slave mode, 10-bit address (SSP1M<3:0> = 0111 or 1111):
R/W-0/0
R/W-1/1
the bit is ignored
SSP1MSK: SSP1 MASK REGISTER
SSP1ADD: MSSP1 ADDRESS AND BAUD RATE REGISTER (I
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
R/W-0/0
R/W-1/1
2
C Slave mode, 10-bit Address
R/W-0/0
R/W-1/1
2
Preliminary
C specification and must be equal to ‘11110’. However, those bits
ADD<7:0>
MSK<7:0>
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
R/W-1/1
OSC
R/W-0/0
PIC16(L)F1824/1828
2
C address match I
2
C address match
R/W-1/1
R/W-0/0
2
C Slave mode, 7-bit address,
2
2
C address match
C address match
R/W-0/0
R/W-1/1
2
C MODE)
DS41419B-page 297
R/W-0/0
R/W-1/1
bit 0
bit 0
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