PIC16F1828-I/P Microchip Technology, PIC16F1828-I/P Datasheet - Page 267
![IC PIC MCU 8BIT 14KB FLSH 20PDIP](/photos/19/6/190621/4696161_sml.jpg)
PIC16F1828-I/P
Manufacturer Part Number
PIC16F1828-I/P
Description
IC PIC MCU 8BIT 14KB FLSH 20PDIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheets
1.PIC16F722-ISS.pdf
(8 pages)
2.PIC16F1826-IP.pdf
(40 pages)
3.PIC16F1824-ISL.pdf
(2 pages)
4.PIC16F1824-ISL.pdf
(419 pages)
5.PIC16F1824-ISL.pdf
(10 pages)
Specifications of PIC16F1828-I/P
Core Size
8-Bit
Program Memory Size
7KB (4K x 14)
Core Processor
PIC
Speed
32MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-DIP (0.300", 7.62mm)
Controller Family/series
PIC16F
No. Of I/o's
18
Eeprom Memory Size
256Byte
Ram Memory Size
256Byte
Cpu Speed
32MHz
No. Of Timers
5
Processor Series
PIC16F
Core
PIC
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F1828-I/P
Manufacturer:
IXYS
Quantity:
143
- PIC16F722-ISS PDF datasheet
- PIC16F1826-IP PDF datasheet #2
- PIC16F1824-ISL PDF datasheet #3
- PIC16F1824-ISL PDF datasheet #4
- PIC16F1824-ISL PDF datasheet #5
- Current page: 267 of 419
- Download datasheet (4Mb)
25.5.3.3
Setting the AHEN bit of the SSP1CON3 register
enables additional clock stretching and interrupt gen-
eration after the 8th falling edge of a received match-
ing address. Once a matching address has been
clocked in, CKP is cleared and the SSP1IF interrupt is
set.
Figure 25-18
Address Slave Transmission with AHEN enabled.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Slave hardware automatically clears the CKP bit
11. Slave software clears SSP1IF.
12. Slave loads value to transmit to the master into
13. Slave sets CKP bit releasing the clock.
14. Master clocks out the data from the slave and
15. Slave hardware copies the ACK value into the
16. Steps 10-15 are repeated for each byte transmit-
17. If the master sends a not ACK the slave
2010 Microchip Technology Inc.
Note: SSP1BUF cannot be loaded until after the
Note: Master must send a not ACK on the last byte
Bus starts Idle.
Master sends Start condition; the S bit of
SSP1STAT is set; SSP1IF is set if interrupt on
Start detect is enabled.
Master sends matching address with R/W bit
set. After the 8th falling edge of the SCL line the
CKP bit is cleared and SSP1IF interrupt is gen-
erated.
Slave software clears SSP1IF.
Slave software reads ACKTIM bit of SSP1CON3
register, and R/W and D/A of the SSP1STAT
register to determine the source of the interrupt.
Slave reads the address value from the
SSP1BUF register clearing the BF bit.
Slave software decides from this information if it
wishes to ACK or not ACK and sets ACKDT bit
of the SSP1CON2 register accordingly.
Slave sets the CKP bit releasing SCL.
Master clocks in the ACK value from the slave.
and sets SSP1IF after the ACK if the R/W bit is
set.
SSP1BUF setting the BF bit.
sends an ACK value on the 9th SCL pulse.
ACKSTAT bit of the SSP1CON2 register.
ted to the master from the slave.
releases the bus allowing the master to send a
Stop and end the communication.
ACK.
to ensure that the slave releases the SCL
line to receive a Stop.
7-bit Transmission with Address
Hold Enabled
displays a standard waveform of a 7-bit
Preliminary
PIC16(L)F1824/1828
DS41419B-page 267
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