PIC16F1828-I/P Microchip Technology, PIC16F1828-I/P Datasheet - Page 45
![IC PIC MCU 8BIT 14KB FLSH 20PDIP](/photos/19/6/190621/4696161_sml.jpg)
PIC16F1828-I/P
Manufacturer Part Number
PIC16F1828-I/P
Description
IC PIC MCU 8BIT 14KB FLSH 20PDIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheets
1.PIC16F722-ISS.pdf
(8 pages)
2.PIC16F1826-IP.pdf
(40 pages)
3.PIC16F1824-ISL.pdf
(2 pages)
4.PIC16F1824-ISL.pdf
(419 pages)
5.PIC16F1824-ISL.pdf
(10 pages)
Specifications of PIC16F1828-I/P
Core Size
8-Bit
Program Memory Size
7KB (4K x 14)
Core Processor
PIC
Speed
32MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-DIP (0.300", 7.62mm)
Controller Family/series
PIC16F
No. Of I/o's
18
Eeprom Memory Size
256Byte
Ram Memory Size
256Byte
Cpu Speed
32MHz
No. Of Timers
5
Processor Series
PIC16F
Core
PIC
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F1828-I/P
Manufacturer:
IXYS
Quantity:
143
- PIC16F722-ISS PDF datasheet
- PIC16F1826-IP PDF datasheet #2
- PIC16F1824-ISL PDF datasheet #3
- PIC16F1824-ISL PDF datasheet #4
- PIC16F1824-ISL PDF datasheet #5
- Current page: 45 of 419
- Download datasheet (4Mb)
3.4
All devices have a 16-level x 15-bit wide hardware
stack (refer to Figures
space is not part of either program or data space. The
PC is PUSHed onto the stack when CALL or CALLW
instructions are executed or an interrupt causes a
branch. The stack is POPed in the event of a RETURN,
RETLW or a RETFIE instruction execution. PCLATH is
not affected by a PUSH or POP operation.
The stack operates as a circular buffer if the STVREN
bit = 0 (Configuration Word 2). This means that after
the stack has been PUSHed sixteen times, the seven-
teenth PUSH overwrites the value that was stored from
the first PUSH. The eighteenth PUSH overwrites the
second PUSH (and so on). The STKOVF and STKUNF
flag bits will be set on an Overflow/Underflow, regard-
less of whether the Reset is enabled.
FIGURE 3-4:
2010 Microchip Technology Inc.
Note 1: There are no instructions/mnemonics
Stack
called PUSH or POP. These are actions
that occur from the execution of the
CALL, CALLW, RETURN, RETLW and
RETFIE instructions or the vectoring to
an interrupt address.
TOSH:TOSL
TOSH:TOSL
ACCESSING THE STACK EXAMPLE 1
3-4
through 3-7). The stack
0x0D
0x0C
0x0E
0x0B
0x0A
0x0F
0x1F
0x09
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
Preliminary
0x0000
3.4.1
The stack is available through the TOSH, TOSL and
STKPTR registers. STKPTR is the current value of the
Stack Pointer. TOSH:TOSL register pair points to the
TOP of the stack. Both registers are read/writable. TOS
is split into TOSH and TOSL due to the 15-bit size of the
PC. To access the stack, adjust the value of STKPTR,
which will position TOSH:TOSL, then read/write to
TOSH:TOSL. STKPTR is 5 bits to allow detection of
overflow and underflow.
During normal program operation, CALL, CALLW and
Interrupts will increment STKPTR while RETLW,
RETURN, and RETFIE will decrement STKPTR. At any
time STKPTR can be inspected to see how much stack
is left. The STKPTR always points at the currently used
place on the stack. Therefore, a CALL or CALLW will
increment the STKPTR and then write the PC, and a
return will unload the PC and then decrement STKPTR.
Reference
of accessing the stack.
Note:
PIC16(L)F1824/1828
STKPTR = 0x1F
STKPTR = 0x1F
Initial Stack Configuration:
After Reset, the stack is empty. The
empty stack is initialized so the Stack
Pointer is pointing at 0x1F. If the Stack
Overflow/Underflow Reset is enabled, the
TOSH/TOSL registers will return ‘0’. If
the Stack Overflow/Underflow Reset is
disabled, the TOSH/TOSL registers will
return the contents of stack address 0x0F.
Figure 3-4
ACCESSING THE STACK
Care should be taken when modifying the
STKPTR while interrupts are enabled.
through
Stack Reset Enabled
(STVREN = 1)
Stack Reset Disabled
(STVREN = 0)
Figure 3-7
DS41419B-page 45
for examples
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