PIC18F24K22-I/SO Microchip Technology, PIC18F24K22-I/SO Datasheet - Page 488

• Manufacturer Part Number: PIC18F24K22-I/SO
• Description: IC PIC MCU 16KB FLASH 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F24K22-I/SO

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 19x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (0.300", 7.50mm Width)
• Controller Family/series: PIC18
• No. Of I/o's: 25
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 64MHz
• No. Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18(L)F2X/4XK22
Timer2
Timer2/4/6 ........................................................................ 175
Timers
Timing Diagrams
DS41412A-page 488
Asynchronous Counter Mode .................................. 165
Clock Source Selection ............................................ 164
Interrupt .................................................................... 168
Operation ................................................................. 164
Operation During Sleep ........................................... 168
Oscillator .................................................................. 165
Prescaler .................................................................. 165
Timer1 Gate
TMR1H Register ...................................................... 163
TMR1L Register ....................................................... 163
Associated registers ................................................. 178
Associated registers ................................................. 178
Timer1
Timer2/4/6
A/D Conversion ........................................................ 461
Acknowledge Sequence .......................................... 248
Asynchronous Reception ......................................... 273
Asynchronous Transmission .................................... 268
Asynchronous Transmission (Back to Back) ........... 269
Auto Wake-up Bit (WUE) During Normal Operation 283
Auto Wake-up Bit (WUE) During Sleep ................... 283
Automatic Baud Rate Calculator .............................. 282
Baud Rate Generator with Clock Arbitration ............ 241
BRG Reset Due to SDA Arbitration During Start
Brown-out Reset (BOR) ........................................... 448
Bus Collision During a Repeated Start Condition
Bus Collision During a Repeated Start Condition
Bus Collision During a Start Condition (SCL = 0) .... 252
Bus Collision During a Stop Condition (Case 1) ...... 254
Bus Collision During a Stop Condition (Case 2) ...... 254
Bus Collision During Start Condition (SDA only) ..... 251
Bus Collision for Transmit and Acknowledge ........... 250
Capture/Compare/PWM (CCP) ................................ 450
CLKO and I/O .......................................................... 447
Clock Synchronization ............................................. 238
Clock/Instruction Cycle .............................................. 74
Comparator Output .................................................. 307
EUSART Synchronous Receive (Master/Slave) ...... 460
EUSART Synchronous Transmission
Example SPI Master Mode (CKE = 0) ..................... 451
Example SPI Master Mode (CKE = 1) ..................... 452
Example SPI Master Mode Timing .......................... 451
Example SPI Slave Mode (CKE = 0) ....................... 453
Example SPI Slave Mode (CKE = 1) ....................... 454
External Clock (All Modes except PLL) .................... 445
Fail-Safe Clock Monitor (FSCM) ................................ 45
First Start Bit Timing ................................................ 242
Full-Bridge PWM Output .......................................... 195
Half-Bridge PWM Output ................................. 193, 199
High/Low-Voltage Detect Characteristics ................ 442
High-Voltage Detect Operation (VDIRMAG = 1) ...... 348
I
2
C Bus Data ............................................................ 456
Reading and Writing ........................................ 165
Selecting Source .............................................. 166
T1CON ............................................................. 172
T1GCON .......................................................... 173
TXCON ............................................................ 177
Condition .......................................................... 252
(Case 1) ........................................................... 253
(Case 2) ........................................................... 253
(Master/Slave) .................................................. 460
Preliminary
Timing Diagrams and Specifications ............................... 445
I
I
I
I
Internal Oscillator Switch Timing ............................... 43
Low-Voltage Detect Operation (VDIRMAG = 0) ...... 347
Master SSP I
Master SSP I
PWM Auto-shutdown ............................................... 198
PWM Direction Change ........................................... 196
PWM Direction Change at Near 100% Duty Cycle .. 197
PWM Output (Active-High) ...................................... 191
PWM Output (Active-Low) ....................................... 192
Repeat Start Condition ............................................ 243
Reset, Watchdog Timer (WDT), Oscillator Start-up
Send Break Character Sequence ............................ 284
Slow Rise Time (MCLR Tied to V
SPI Mode (Master Mode) ......................................... 215
Synchronous Reception (Master Mode, SREN) ...... 289
Synchronous Transmission ..................................... 286
Synchronous Transmission (Through TXEN) .......... 286
Time-out Sequence on POR w/PLL Enabled
Time-out Sequence on Power-up (MCLR
Time-out Sequence on Power-up (MCLR
Time-out Sequence on Power-up (MCLR
Timer0 and Timer1 External Clock .......................... 449
Timer1 Incrementing Edge ...................................... 169
Transition for Entry to SEC_RUN Mode .................... 49
Transition for Entry to Sleep Mode ............................ 51
Transition for Wake from Sleep (HSPLL) .................. 52
Transition from RC_RUN Mode to PRI_RUN Mode .. 50
Transition from SEC_RUN Mode to
Transition Timing for Entry to Idle Mode .................... 52
Transition Timing for Wake from Idle to Run Mode ... 53
A/D Conversion Requirements ................................ 462
Capture/Compare/PWM Requirements ................... 451
CLKO and I/O Requirements ................................... 447
EUSART Synchronous Receive Requirements ....... 460
EUSART Synchronous Transmission
Example SPI Mode Requirements
External Clock Requirements .................................. 445
I
I
Master SSP I
Master SSP I
PLL Clock ................................................................ 446
Reset, Watchdog Timer, Oscillator Start-up Timer,
Timer0 and Timer1 External Clock Requirements ... 449
2
2
2
2
2
2
C Bus Start/Stop Bits ............................................ 455
C Master Mode (7 or 10-Bit Transmission) ........... 245
C Master Mode (7-Bit Reception) .......................... 247
C Stop Condition Receive or Transmit Mode ........ 249
C Bus Data Requirements (Slave Mode) .............. 457
C Bus Start/Stop Bits Requirements
Firmware Restart ............................................. 198
V
(MCLR Tied to V
Not Tied to V
Not Tied to V
Tied to V
PRI_RUN Mode (HSPLL) .................................. 49
Requirements .................................................. 460
(Master Mode, CKE = 0) .................................. 452
(Master Mode, CKE = 1) .................................. 453
(Slave Mode, CKE = 0) .................................... 454
(Slave Mode, CKE = 1) .................................... 455
(Slave Mode) ................................................... 456
Power-up Timer and Brown-out Reset
Requirements .................................................. 448
Timer (OST), Power-up Timer (PWRT) .......... 448
DD
Rise > T
2
2
2
2
DD
C Bus Data ........................................ 458
C Bus Start/Stop Bits ........................ 458
C Bus Data Requirements ................ 459
C Bus Start/Stop Bits Requirements . 458
, V
PWRT
DD
DD
DD
, Case 1) ................................... 64
, Case 2) ................................... 65
 2010 Microchip Technology Inc.
DD
Rise < T
) ............................................ 65
) .......................................... 66
PWRT
DD
,
) ....................... 64