PIC18F26K22-I/SO Microchip Technology, PIC18F26K22-I/SO Datasheet - Page 392
PIC18F26K22-I/SO
Manufacturer Part Number
PIC18F26K22-I/SO
Description
IC PIC MCU 64KB FLASH 28SOIC
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC16F722-ISS.pdf
(8 pages)
2.PIC18F26J13-ISS.pdf
(496 pages)
3.PIC18F24K22-ISP.pdf
(494 pages)
Specifications of PIC18F26K22-I/SO
Core Size
8-Bit
Program Memory Size
64KB (32K x 16)
Core Processor
PIC
Speed
64MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 19x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (0.300", 7.50mm Width)
Controller Family/series
PIC18
No. Of I/o's
25
Eeprom Memory Size
1KB
Ram Memory Size
3896Byte
Cpu Speed
64MHz
No. Of Timers
7
Processor Series
PIC18F
Core
PIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F26K22-I/SO
Manufacturer:
NXP
Quantity:
928
Part Number:
PIC18F26K22-I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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PIC18(L)F2X/4XK22
MOVFF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
1st word (source)
2nd word (destin.)
Description:
Words:
Cycles:
Example:
DS41412D-page 392
Q Cycle Activity:
Before Instruction
After Instruction
Decode
Decode
REG1
REG2
REG1
REG2
Q1
No dummy
register ‘f’
operation
Move f to f
MOVFF f
0 f
0 f
(f
None
The contents of source register ‘f
moved to destination register ‘f
Location of source ‘f
in the 4096-byte data space (000h to
FFFh) and location of destination ‘f
can also be anywhere from 000h to
FFFh.
Either source or destination can be W
(a useful special situation).
MOVFF
transferring a data memory location to a
peripheral register (such as the transmit
buffer or an I/O port).
The MOVFF instruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register.
2
2 (3)
MOVFF
s
Read
) f
(src)
read
1100
1111
Q2
No
=
=
=
=
s
d
4095
4095
d
is particularly useful for
33h
11h
33h
33h
s
REG1, REG2
,f
ffff
ffff
d
operation
Process
Data
Q3
No
s
’ can be anywhere
ffff
ffff
register ‘f’
operation
(dest)
Write
d
Q4
No
fff
fff
’.
s
’ are
d
Preliminary
f
f
’
s
d
MOVLB
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
BSR Register =
BSR Register =
Q1
Move literal to low nibble in BSR
MOVLW k
0 k 255
k
None
The eight-bit literal ‘k’ is loaded into the
Bank Select Register (BSR). The value
of BSR<7:4> always remains ‘
regardless of the value of k
1
1
MOVLB
literal ‘k’
Read
0000
Q2
BSR
2010 Microchip Technology Inc.
02h
05h
0001
5
Process
Data
Q3
kkkk
Write literal
7
‘k’ to BSR
:k
4
0
.
Q4
’,
kkkk
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