XA3S500E-4FT256Q Xilinx Inc, XA3S500E-4FT256Q Datasheet - Page 11
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XA3S500E-4FT256Q
Manufacturer Part Number
XA3S500E-4FT256Q
Description
IC FPGA SPARTAN-3E 256FPBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3E XAr
Datasheet
1.XA3S100E-4VQG100I.pdf
(37 pages)
Specifications of XA3S500E-4FT256Q
Number Of Logic Elements/cells
10476
Number Of Labs/clbs
1164
Total Ram Bits
368640
Number Of I /o
190
Number Of Gates
500000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 125°C
Package / Case
256-LBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XA3S500E-4FT256Q
Manufacturer:
XILINX
Quantity:
300
Part Number:
XA3S500E-4FT256Q
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Single-Ended I/O Standards
Table 9: Recommended Operating Conditions for User I/Os Using Single-Ended Standards
DS635 (v2.0) September 9, 2009
Product Specification
Notes:
1.
2.
3.
4.
5.
6.
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
PCI33_3
HSTL_I_18
HSTL_III_18
SSTL18_I
SSTL2_I
IOSTANDARD
Descriptions of the symbols used in this table are as follows:
V
V
V
V
The V
For device operation, the maximum signal voltage (V
There is approximately 100 mV of hysteresis on inputs using LVCMOS33 and LVCMOS25 I/O standards.
All Dedicated pins (PROG_B, DONE, TCK, TDI, TDO, and TMS) use the LVCMOS25 standard and draw power from the V
The Dual-Purpose configuration pins use the LVCMOS standard before the User mode. When using these pins as part of a standard 2.5V
configuration interface, apply 2.5V to the V
For information on PCI IP solutions, see
CCO
REF
IL
IH
Attribute
– the input voltage that indicates a Low logic level
– the input voltage that indicates a High logic level
– the reference voltage for setting the input switching threshold
– the supply voltage for output drivers
CCO
R
(4)
(4,5)
rails supply only output drivers, not input circuits.
Min (V)
1.65
3.0
3.0
2.3
1.4
1.1
3.0
1.7
1.7
1.7
2.3
V
CCO
Nom (V)
for Drivers
3.3
3.3
2.5
1.8
1.5
1.2
3.3
1.8
1.8
1.8
2.5
www.xilinx.com/pci.
CCO
lines of Banks 0, 1, and 2 at power-on as well as throughout configuration.
Max (V)
(2)
3.465
3.465
3.465
1.95
2.7
1.6
1.3
1.9
1.9
1.9
2.7
IH
max) may be as high as V
www.xilinx.com
Min (V)
0.833
1.15
0.8
-
V
these I/O standards
REF
Nom (V)
is not used for
0.900
V
1.25
0.9
1.1
REF
IN
max. See Table 72 in DS312.
Max (V)
0.969
1.35
1.1
-
V
V
0.3 * V
V
V
REF
REF
Max (V)
REF
REF
V
0.8
0.8
0.7
0.4
0.4
0.4
- 0.125
- 0.125
IL
- 0.1
- 0.1
CCO
CCAUX
V
V
0.5 * V
V
V
REF
REF
REF
REF
Min (V)
V
2.0
2.0
1.7
0.8
0.8
0.7
rail (2.5V).
+ 0.125
+ 0.125
IH
+ 0.1
+ 0.1
CCO
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