XA3S500E-4FT256Q Xilinx Inc, XA3S500E-4FT256Q Datasheet - Page 23
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XA3S500E-4FT256Q
Manufacturer Part Number
XA3S500E-4FT256Q
Description
IC FPGA SPARTAN-3E 256FPBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3E XAr
Datasheet
1.XA3S100E-4VQG100I.pdf
(37 pages)
Specifications of XA3S500E-4FT256Q
Number Of Logic Elements/cells
10476
Number Of Labs/clbs
1164
Total Ram Bits
368640
Number Of I /o
190
Number Of Gates
500000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 125°C
Package / Case
256-LBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XA3S500E-4FT256Q
Manufacturer:
XILINX
Quantity:
300
Part Number:
XA3S500E-4FT256Q
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Table 24: 18 x 18 Embedded Multiplier Timing (Continued)
Block RAM Timing
Table 25: Block RAM Timing
DS635 (v2.0) September 9, 2009
Product Specification
Notes:
1.
2.
3.
Clock Frequency
F
Clock-to-Output Times
T
Setup Times
T
T
T
T
Hold Times
T
T
T
T
MULT
BCKO
BACK
BDCK
BECK
BWCK
BCKA
BCKD
BCKE
BCKW
Symbol
Symbol
Combinatorial delay is less and pipelined performance is higher when multiplying input data with less than 18 bits.
The PREG register is typically used in both single-stage and two-stage pipelined multiplier implementations.
Input registers AREG or BREG are typically used when inferring a two-stage multiplier.
R
When reading from block RAM, the delay from the active transition
at the CLK input to data appearing at the DOUT output
Setup time for the ADDR inputs before the active transition at the
CLK input of the block RAM
Setup time for data at the DIN inputs before the active transition at
the CLK input of the block RAM
Setup time for the EN input before the active transition at the CLK
input of the block RAM
Setup time for the WE input before the active transition at the CLK
input of the block RAM
Hold time on the ADDR inputs after the active transition at the CLK
input
Hold time on the DIN inputs after the active transition at the CLK
input
Hold time on the EN input after the active transition at the CLK input
Hold time on the WE input after the active transition at the CLK input
Internal operating frequency for a two-stage 18x18 multiplier using the
AREG and BREG input registers and the PREG output register
Description
Description
www.xilinx.com
(1)
0.38
0.23
0.77
1.26
0.14
0.13
Min
-4 Speed Grade
0
0
-
-4 Speed Grade
Min
0
Max
2.82
-
-
-
-
-
-
-
-
Max
240
Units
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
23