XC4VLX40-10FF1148I Xilinx Inc, XC4VLX40-10FF1148I Datasheet - Page 26
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XC4VLX40-10FF1148I
Manufacturer Part Number
XC4VLX40-10FF1148I
Description
IC FPGA VIRTEX-4LX 1148FFBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VLX40-10FF1148I
Number Of Logic Elements/cells
41472
Number Of Labs/clbs
4608
Total Ram Bits
1769472
Number Of I /o
640
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1148-BBGA, FCBGA
Package
1148FCBGA
Family Name
Virtex®-4
Device Logic Units
41472
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
640
Ram Bits
1769472
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC4VLX40-10FF1148I
Manufacturer:
XC
Quantity:
1 238
Company:
Part Number:
XC4VLX40-10FF1148I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Input/Output Logic Switching Characteristics
Table 32: ILOGIC Switching Characteristics
DS302 (v3.7) September 9, 2009
Product Specification
Notes:
1.
Setup/Hold
Combinatorial
Sequential Delays
Set/Reset
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
Recorded at 0 tap value. Refer to Timing Report for other values.
ICE1CK
ICECK
IRSTCK
IINCCK
ISRCK
IDOCK
IDOCKD
IDI
IDID
IDLO
IDLOD
ICKQ
ICE1Q
RQ
GSRQ
RPW
Symbol
/
/
/
/
/
T
/
T
T
/
T
T
T
ICKCE
ICKSR
T
IOCKD
ICKINC
ICKCE1
ICKRST
IOCKDD
CE1 pin Setup/Hold with respect to CLK
DLYCE pin Setup/Hold with respect to C
DLYRST pin Setup/Hold with respect to C
DLYINC pin Setup/Hold with respect to C
SR/REV pin Setup/Hold with respect to CLK
D pin Setup/Hold with respect to CLK without Delay
D pin Setup/Hold with respect to CLK
(IOBDELAY_TYPE = DEFAULT)
D pin Setup/Hold with respect to CLK
(IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0)
D pin to O pin propagation delay, no Delay
D pin to O pin propagation delay
(IOBDELAY_TYPE = DEFAULT)
D pin to O pin propagation delay
(IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0)
D pin to Q1 pin using flip-flop as a latch without Delay
D pin to Q1 pin using flip-flop as a latch
(IOBDELAY_TYPE = DEFAULT)
D pin to Q1 pin using flip-flop as a latch
(IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0)
CLK to Q outputs
CE1 pin to Q1 using flip-flop as a latch, propagation delay
SR/REV pin to OQ/TQ out
Global Set/Reset to Q outputs
Minimum Pulse Width, SR/REV inputs
Description
www.xilinx.com
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
(1)
(1)
(1)
–0.23
–0.03
–0.56
–0.10
–5.99
–0.63
0.58
0.16
0.11
0.37
0.01
0.36
1.15
0.24
6.64
0.81
0.17
6.00
0.74
0.50
6.90
1.07
0.53
0.90
1.70
1.54
0.53
-12
Speed Grade
–0.23
–0.02
–0.56
–0.10
–5.99
–0.63
0.66
0.19
0.13
0.45
0.01
0.43
1.33
0.28
7.63
0.87
0.20
6.91
0.79
0.59
7.94
1.18
0.60
1.06
2.03
1.73
0.59
-11
–0.23
–0.02
–0.56
–0.10
–5.99
–0.63
0.79
0.23
0.16
0.54
0.01
0.51
1.59
0.34
8.84
1.09
0.24
7.96
0.99
0.71
9.21
1.45
0.72
1.27
2.44
2.03
0.70
-10
Units
Min
ns,
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
26