XC4VLX40-10FF1148I Xilinx Inc, XC4VLX40-10FF1148I Datasheet - Page 37
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XC4VLX40-10FF1148I
Manufacturer Part Number
XC4VLX40-10FF1148I
Description
IC FPGA VIRTEX-4LX 1148FFBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VLX40-10FF1148I
Number Of Logic Elements/cells
41472
Number Of Labs/clbs
4608
Total Ram Bits
1769472
Number Of I /o
640
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1148-BBGA, FCBGA
Package
1148FCBGA
Family Name
Virtex®-4
Device Logic Units
41472
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
640
Ram Bits
1769472
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC4VLX40-10FF1148I
Manufacturer:
XC
Quantity:
1 238
Company:
Part Number:
XC4VLX40-10FF1148I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Table 43: Configuration Switching Characteristics (Continued)
DS302 (v3.7) September 9, 2009
Product Specification
Notes:
1.
2.
Boundary-Scan Port Timing Specifications
Dynamic Reconfiguration Port (DRP) for DCM
T
T
T
F
F
CLKIN_FREQ_DLL_HF_MS_MAX
T
T
T
T
T
T
T
do not apply to the BUFGMUX_VIRTEX4 primitive that assures glitch-free operation. The other global clock setup and hold times are optional; only
needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switching between clocks.
DO holds until the next DRP operation.
TAPTCK
TCKTAP
TCKTDO
TCK
TCKB
DMCCK_DADDR
DMCCK_DI
DMCCK_DEN
DMCCK_DWE
DMCKO_DO
DMCKO_DRDY
BCCCK_CE
/T
and T
DMCKC_DI
/T
/T
Symbol
DMCKC_DEN
DMCKC_DWE
/T
BCCKC_CE
DMCKC_DADDR
must be satisfied to assure glitch-free operation of the global clock when switching between clocks. These parameters
TMS and TDI Setup time before TCK
TMS and TDI Hold time after TCK
TCK falling edge to TDO output valid
Maximum configuration TCK clock
frequency
Maximum Boundary-Scan TCK clock
frequency
Maximum frequency for DCLK
DADDR Setup/Hold time
DI Setup/Hold time
DEN Setup/Hold time
DWE Setup/Hold time
CLK to out of DO
CLK to out of DRDY
www.xilinx.com
Description
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
(2)
0.54
0.00
0.54
0.00
0.58
0.00
0.58
0.00
0.68
-12
500
1.0
2.0
6.0
66
50
0
Speed Grade
0.63
0.00
0.63
0.00
0.58
0.00
0.58
0.00
0.80
-11
450
1.0
2.0
6.0
66
50
0
0.72
0.00
0.72
0.00
0.58
0.00
0.58
0.00
0.92
-10
400
1.0
2.0
6.0
66
50
0
MHz, Max
MHz, Max
MHz, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Min
ns, Min
Units
37