NUC120LE3AN Nuvoton Technology Corporation of America, NUC120LE3AN Datasheet - Page 473
![IC MCU 32BIT 128KB FLASH 48LQFP](/photos/28/73/287353/nuc120le3an_sml.jpg)
NUC120LE3AN
Manufacturer Part Number
NUC120LE3AN
Description
IC MCU 32BIT 128KB FLASH 48LQFP
Manufacturer
Nuvoton Technology Corporation of America
Series
NuMicro™r
Specifications of NUC120LE3AN
Core Processor
ARM Cortex-M0
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, LVD, POR, PS2, PWM, WDT
Number Of I /o
31
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
NUC120LE3AN
Manufacturer:
Nuvoton Technology Corporation of America
Quantity:
10 000
Part Number:
NUC120LE3AN
Manufacturer:
NUVOTON
Quantity:
20 000
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5.15.6 Register Description
I
Register
I2S_CON
Bits
[31:22]
[21]
[20]
[19]
[18]
2
S Control Register (I2S_CON)
Reserved
MCLKEN
FORMAT
31
23
15
7
NuMicro™ NUC100 Series Technical Reference Manual
Offset
I2S_BA+0x00
Descriptions
Reserved
RXDMA
TXDMA
CLR_RXFIFO
CLR_TXFIFO
Reserved
MONO
30
22
14
6
RXTH[2:0]
RXDMA
R/W
R/W
Reserved
Enable Receive DMA
When RX DMA is enabled, I
SRAM if FIFO is not empty.
1 = Enable RX DMA
0 = Disable RX DMA
Enable Transmit DMA
When TX DMA is enables, I
FIFO if FIFO is not full.
1 = Enable TX DMA
0 = Disable TX DMA
Clear Receive FIFO
Write 1 to clear receive FIFO, internal pointer is reset to FIFO start point, and
RXFIFO_LEVEL[3:0] returns to zero and receive FIFO becomes empty.
This bit is cleared by hardware automatically, read it return zero.
Clear Transmit FIFO
Write 1 to clear transmit FIFO, internal pointer is reset to FIFO start point, and
TXFIFO_LEVEL[3:0] returns to zero and transmit FIFO becomes empty but data in
transmit FIFO is not changed.
This bit is clear by hardware automatically, read it return zero.
29
21
13
5
WORDWIDTH
Description
I
2
S Control Register
TXDMA
28
20
12
4
- 473 -
Reserved
CLR_RXFIFO CLR_TXFIFO
2
2
S request DMA to transfer data from SRAM to transmit
MUTE
S requests DMA to transfer data from receive FIFO to
27
19
11
3
Publication Release Date: Oct 22, 2010
TXTH[2:0]
RXEN
26
18
10
2
LCHZCEN
TXEN
25
17
9
1
Revision V1.06
Reset Value
0x0000_0000
RCHZCEN
SLAVE
I2SEN
24
16
8
0
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