NUC120LE3AN Nuvoton Technology Corporation of America, NUC120LE3AN Datasheet - Page 531
![IC MCU 32BIT 128KB FLASH 48LQFP](/photos/28/73/287353/nuc120le3an_sml.jpg)
NUC120LE3AN
Manufacturer Part Number
NUC120LE3AN
Description
IC MCU 32BIT 128KB FLASH 48LQFP
Manufacturer
Nuvoton Technology Corporation of America
Series
NuMicro™r
Specifications of NUC120LE3AN
Core Processor
ARM Cortex-M0
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, LVD, POR, PS2, PWM, WDT
Number Of I /o
31
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
NUC120LE3AN
Manufacturer:
Nuvoton Technology Corporation of America
Quantity:
10 000
Part Number:
NUC120LE3AN
Manufacturer:
NUVOTON
Quantity:
20 000
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PDMA Shared Buffer FIFO 0 (PDMA_SBUF0_cx)
Register
PDMA_SBUF0_c0 PDMA_BA_ch0+0x080 R
PDMA_SBUF0_c1 PDMA_BA_ch1+0x180 R
PDMA_SBUF0_c2 PDMA_BA_ch2+0x280 R
PDMA_SBUF0_c3 PDMA_BA_ch3+0x380 R
PDMA_SBUF0_c4 PDMA_BA_ch4+0x480 R
PDMA_SBUF0_c5 PDMA_BA_ch5+0x580 R
PDMA_SBUF0_c6 PDMA_BA_ch6+0x680 R
PDMA_SBUF0_c7 PDMA_BA_ch7+0x780 R
PDMA_SBUF0_c8 PDMA_BA_ch8+0x880 R
Notice: Low Density only support PDMA channel 0.
Bits
[31:0]
31
23
15
7
NuMicro™ NUC100 Series Technical Reference Manual
Descriptions
PDMA_SBUF0
Offset
30
22
14
6
PDMA Shared Buffer FIFO 0 (Read Only)
Each channel has its own 1 words internal buffer.
29
21
13
5
R/W
PDMA_SBUF0 [31:24]
PDMA_SBUF0 [23:16]
PDMA_SBUF0 [15:8]
PDMA_SBUF0 [7:0]
Description
PDMA Shared Buffer FIFO 0 Register CH0
PDMA Shared Buffer FIFO 0 Register CH1
PDMA Shared Buffer FIFO 0 Register CH2
PDMA Shared Buffer FIFO 0 Register CH3
PDMA Shared Buffer FIFO 0 Register CH4
PDMA Shared Buffer FIFO 0 Register CH5
PDMA Shared Buffer FIFO 0 Register CH6
PDMA Shared Buffer FIFO 0 Register CH7
PDMA Shared Buffer FIFO 0 Register CH8
28
20
12
4
- 531 -
27
19
11
3
Publication Release Date: Oct 22, 2010
26
18
10
2
25
17
9
1
Revision V1.06
Reset Value
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
24
16
8
0
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