ATTINY861V-10SUR Atmel, ATTINY861V-10SUR Datasheet - Page 12
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ATTINY861V-10SUR
Manufacturer Part Number
ATTINY861V-10SUR
Description
IC MCU AVR 8K FLASH 10MHZ 20SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY861V-10SUR
Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Part Number:
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Manufacturer:
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4.7
12
Reset and Interrupt Handling
ATtiny261/461/861
Figure 4-4.
Figure 4-5
operation using two register operands is executed, and the result is stored back to the destina-
tion register.
Figure 4-5.
The AVR provides several different interrupt sources. These interrupts and the separate Reset
Vector each have a separate Program Vector in the Program memory space. All interrupts are
assigned individual enable bits which must be written logic one together with the Global Interrupt
Enable bit in the Status Register in order to enable the interrupt.
The lowest addresses in the Program memory space are by default defined as the Reset and
Interrupt Vectors. The complete list of vectors is shown in
determines the priority levels of the different interrupts. The lower the address the higher is the
priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request
0.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis-
abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled
interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a
Return from Interrupt instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that sets the
Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vec-
tor in order to execute the interrupt handling routine, and hardware clears the corresponding
Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s)
2nd Instruction Execute
Register Operands Fetch
3rd Instruction Execute
1st Instruction Execute
ALU Operation Execute
2nd Instruction Fetch
3rd Instruction Fetch
4th Instruction Fetch
1st Instruction Fetch
Total Execution Time
Result Write Back
shows the internal timing concept for the Register File. In a single clock cycle an ALU
The Parallel Instruction Fetches and Instruction Executions
Single Cycle ALU Operation
clk
clk
CPU
CPU
T1
T1
T2
T2
“Interrupts” on page
T3
T3
50. The list also
2588E–AVR–08/10
T4
T4
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