ATTINY861V-10SUR Atmel, ATTINY861V-10SUR Datasheet - Page 27
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ATTINY861V-10SUR
Manufacturer Part Number
ATTINY861V-10SUR
Description
IC MCU AVR 8K FLASH 10MHZ 20SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY861V-10SUR
Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Part Number:
ATTINY861V-10SUR
Manufacturer:
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2588E–AVR–08/10
The fast peripheral clock, clk
prescaled version of the PLL output, clk
a detailed illustration on the PLL clock system.
Figure 6-3.
The internal PLL is enabled when CKSEL fuse bits are programmed to ‘0001’and the PLLE bit of
PLLCSR is set. The internal oscillator and the PLL are switched off in power down and stand-by
sleep modes.
When the LSM bit of PLLCSR is set, the PLL switches from using the output of the internal 8
MHz oscillator to using the output divided by two. The frequency of the fast peripheral clock is
effectively divided by two, resulting in a clock frequency of 32 MHz. The LSM bit can not be set if
PLL
Since the PLL is locked to the output of the internal 8 MHz oscillator, adjusting the oscillator fre-
quency via the OSCCAL register also changes the frequency of the fast peripheral clock. It is
possible to adjust the frequency of the internal oscillator to well above 8 MHz but the fast periph-
eral clock will saturate and remain oscillating at about 85 MHz. In this case the PLL is no longer
locked to the internal oscillator clock signal. Therefore, in order to keep the PLL in the correct
operating range, it is recommended to program the OSCCAL registers such that the oscillator
frequency does not exceed 8 MHz.
The PLOCK bit in PLLCSR is set when PLL is locked.
Programming CKSEL fuse bits to ‘0001’, the PLL output divided by four will be used as a system
clock, as shown in
Table 6-4.
XTAL1
XTAL2
CLK
is used as a system clock.
OSCCAL
OSCILLATORS
OSCILLATOR
8 MHz
CKSEL3:0
PCK Clocking System
PLLCK Operating Modes
0001
Table
LSM
6-4.
1/2
PCK
4 MHz
8 MHz
, can be selected as the clock source for Timer/Counter1 and a
PLL
, can be selected as system clock. See
PLLE
PLL
8x
64 / 32 MHz
Nominal Frequency
DETECTOR
1/4
LOCK
16 MHz
16 MHz
8 MHz
CKSEL3:0
PRESCALER
CLKPS3:0
Figure 6-3
PLOCK
clk
clk
PCK
PLL
for
27
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