ATTINY861V-10SUR Atmel, ATTINY861V-10SUR Datasheet - Page 132
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ATTINY861V-10SUR
Manufacturer Part Number
ATTINY861V-10SUR
Description
IC MCU AVR 8K FLASH 10MHZ 20SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY861V-10SUR
Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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13.4
13.4.1
13.4.2
13.4.3
13.4.4
13.4.5
13.5
13.5.1
132
Alternative USI Usage
Register Descriptions
ATtiny261/461/861
Half-Duplex Asynchronous Data Transfer
4-Bit Counter
12-Bit Timer/Counter
Edge Triggered External Interrupt
Software Interrupt
USIDR – USI Data Register
The flexible design of the USI allows it to be used for other tasks when serial communication is
not needed. Below are some examples.
Using the USI Data Register in three-wire mode it is possible to implement a more compact and
higher performance UART than by software, only.
The 4-bit counter can be used as a stand-alone counter with overflow interrupt. Note that if the
counter is clocked externally, both clock edges will increment the counter value.
Combining the 4-bit USI counter with one of the 8-bit timer/counters creates a 12-bit counter.
By setting the counter to maximum value (F) it can function as an additional external interrupt.
The Overflow Flag and Interrupt Enable bit are then used for the external interrupt. This feature
is selected by the USICS1 bit.
The counter overflow interrupt can be used as a software interrupt triggered by a clock strobe.
The USI Data Register can be accessed directly.
Depending on the USICS1:0 bits of the USI Control Register a (left) shift operation may be per-
formed. The shift operation can be synchronised to an external clock edge, to a Timer/Counter0
Compare Match, or directly to software via the USICLK bit. If a serial clock occurs at the same
cycle the register is written, the register will contain the value written and no shift is performed.
Note that even when no wire mode is selected (USIWM1:0 = 0) both the external data input
(DI/SDA) and the external clock input (USCK/SCL) can still be used by the USI Data Register.
The output pin (DO or SDA, depending on the wire mode) is connected via the output latch to
the most significant bit (bit 7) of the USI Data Register. The output latch ensures that data input
is sampled and data output is changed on opposite clock edges. The latch is open (transparent)
during the first half of a serial clock cycle when an external clock source is selected (USICS1 =
1) and constantly open when an internal clock source is used (USICS1 = 0). The output will be
changed immediately when a new MSB is written as long as the latch is open.
Note that the Data Direction Register bit corresponding to the output pin must be set to one in
order to enable data output from the USI Data Register.
Bit
0x0F (0x2F)
Read/Write
Initial Value
7
MSB
R/W
0
6
R/W
0
5
R/W
0
4
R/W
0
3
R/W
0
2
0
R/W
1
R/W
0
0
LSB
R/W
0
2588E–AVR–08/10
USIDR
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