AT89LP52-20PU Atmel, AT89LP52-20PU Datasheet - Page 63

• Manufacturer Part Number: AT89LP52-20PU
• Description: IC MCU 8051 8K FLASH SPI 40PDIP
• Manufacturer: Atmel
• Series: 89LPr

Specifications of AT89LP52-20PU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: Serial
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Figure 14-1. Mode 0 Waveforms (Two-Wire)
3709B–MICRO–12/10
SMOD1 = 0
SM2 = 0
SMOD1 = 1
SM2 = 0
SMOD1 = 0
SM2 = 1
SMOD1 = 1
SM2 = 1
RXD (RX)
RXD (RX)
RXD (RX)
RXD (RX)
RXD (TX)
RXD (TX)
RXD (TX)
RXD (TX)
state of the clock when not currently transmitting/receiving. The SMOD1 bit determines if the
output data is stable for both edges of the clock, or just one.
Table 14-5.
In Two-Wire configuration Mode 0 may be used as a hardware accelerator for software emula-
tion of serial interfaces such as a half-duplex Serial Peripheral Interface (SPI) master in mode
(0,0) or (1,1) or a Two-Wire Interface (TWI) in master mode. An example of Mode 0 emulating a
TWI master device is shown in
are handled in software while the byte transmission is done in hardware. Falling/rising edges on
TXD are created by setting/clearing SM2. Rising/falling edges on RXD are forced by set-
ting/clearing the P3.0 register bit. SM2 and P3.0 must be 1 while the byte is being transferred.
TXD
TXD
TXD
TXD
SM2
0
0
1
1
SMOD1
Mode 0 Clock and Data Modes
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
Clock Idle
1
1
High
High
Low
Low
2
2
Figure
2
2
2
2
2
2
3
3
14-2. In this example, the start, stop, and acknowledge
3
3
3
3
3
3
Negative edge of clock
Negative edge of clock
While clock is high
AT89LP51/52 - Preliminary
While clock is low
Data Changes
4
4
4
4
4
4
4
4
5
5
5
5
5
5
5
5
6
6
6
6
6
6
6
6
Negative edge of clock
Positive edge of clock
Positive edge of clock
Positive edge of clock
7
7
7
7
7
7
7
7
Data Sampled
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