AT89LP52 Atmel Corporation, AT89LP52 Datasheet

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... Input-only (Tristate) • Push-pull CMOS Output • Open-drain • Operating Conditions – 2.4V to 5.5V V Voltage Range CC – -40° 85°C Temperature Range – MHz @ 2.4V–5.5V – MHz @ 4.5V–5.5V 8-bit Microcontroller with 4K/8K Bytes In-System Programmable Flash AT89LP51 AT89LP52 3709D–MICRO–12/11 ...

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Pin Configurations 1.1 40-lead PDIP 1.2 44-lead TQFP (MOSI) P1.5 (MISO) P1.6 AT89LP51/52 2 (T2) P1 VCC (T2 EX) P1 P0.0 (AD0) P1 P0.1 (AD1) P1 P0.2 (AD2) P1 ...

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PLCC 1.4 44-pad VQFN/QFN/MLF 3709D–MICRO–12/11 (MOSI) P1.5 7 (MISO) P1.6 8 (SCK) P1.7 9 RST 10 (RXD) P3.0 11 *NC 12 (TXD) P3.1 13 (INT0) P3.2 14 (INT1) P3.3 15 (T0) P3.4 16 (T1) P3.5 17 MOSI/P1.5 1 ...

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Pin Description Table 1-1. AT89LP51/52 Pin Description Pin Number TQFP PLCC PDIP VQFN ...

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Table 1-1. AT89LP51/52 Pin Description Pin Number TQFP PLCC PDIP VQFN ...

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... Vcc and temperature compensated well enough to ensure proper UART serial communications. Together with the built-in POR and the BOD circuits, you do not need any external components for AT89LP52 to provide the reset and clock functions • All three timer/counters of the AT89LP51/52, Timer 0, Timer 1 and Timer 2, can be configured to toggle a port pin on overflow for clock/waveform generation ...

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Block Diagram Figure 2-1. Crystal or Resonator 2.2 System Configuration The AT89LP51/52 supports several system configuration options. Nonvolatile options are set through user fuses that must be programmed through the flash programming interface. Volatile options are controlled by software ...

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... Fast mode allows greater performance, but with some differences in behavior. The major enhancements from the AT89S51/52 are outlined in the following paragraphs and may be useful to users migrating to the AT89LP51/52 from older devices. A summary of the differences between Compatibility and Fast modes is given in tion note “Migrating from AT89S52 to AT89LP52.” AT89LP51/52 8 User Configuration Fuses ...

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Instruction Execution In Compatibility mode the AT89LP51/52 CPU uses the six-state machine cycle of the standard 8051 where instruction bytes are fetched every three system clock cycles. Execution times in this mode are identical to AT89S51/52. For greater performance ...

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Interrupt Handling With the addition of the IPH register, the AT89LP51/52 provides four levels of interrupt priority for greater flexibility in handling multiple interrupts. Also, Fast mode allows for faster interrupt response due to the shorter instruction execution times. ...

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... Constant tables can be allocated within the entire 64K Figure AT89LP51/52 Compatibility Fast Prescaler Rate System Clock 12 AUXR WDTCON Table 3-1. Range 00H–7FH 00H–FFH 80H–FFH 0000H–00FFH 0100H–FFFFH 0000H–0FFFH (AT89LP51) 0000H–1FFFH (AT89LP52) 2000H–FFFFH (AT89LP51) 1000H–FFFFH (AT89LP52) 0000H–01FFH 3- ...

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... ROM using shows the timing of the external program memory interface. ALE is emitted at a con- Executing from External Program Memory AT89LP P1 P0 ALE P2 P3 PSEN AT89LP52 User Signature Array SIGEN=1 Atmel Signature Array External Program Memory (XCODE: 56KB) SIGEN=0 Internal Program Memory ...

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Figure 3-3. In order for Fast mode to fetch externally, two wait states must be inserted for every clock cycle, increasing the instruction execution time by a factor of 3. However, due to other optimizations, external Fast mode instructions may ...

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The User Signature Array may also be modified by the In-Application Programming interface. When IAP = 1 and SIGEN = 1, MOVX @DPTR instructions will access the array (See 3.2 Internal Data Memory The AT89LP51/52 contains ...

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CPU can access them. The AT89LP51/52 includes 256 bytes of nonvolatile Flash data memory (FDATA). 3.3.1 XDATA The external data memory space can accommodate up to 64KB of external memory. The AT89LP51/52 uses the ...

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DMEN = 0. FDATA can be accessed only by 16-bit (MOVX @DPTR) addresses. MOVX @Ri instructions to the FDATA address range will access external memory. Addresses above the FDATA range are mapped to XDATA. 3.3.2.1 Write Protocol ...

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The LDPG bit (MEMCON.5) allows multiple data bytes to be loaded to the temporary page buf- fer. While LDPG = 1, MOVX @DPTR,A instructions will load data to the page buffer, but will not start a write sequence. Note that ...

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The stored value of the high half page must be written without auto-erase after the programming of the low half page completes. This method reduces the amount of RAM required; however, ...

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Figure 3-10. External Data Memory 16-bit Linear Address Mode Figure 3-11 using an 8-bit paged address. Port 0 serves as a multiplexed address/data bus to the RAM. The ALE strobe is used to latch the address byte into an external ...

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Table 3-3. – Auxiliary Control Register AUXR AUXR = 8EH Not Bit Addressable – – Bit 7 6 Symbol Function WDT Disable during Idle WDIDLE halts counting in Idle mode. (1) Disable Reset Output DISRTO When DISRTO = 1 the ...

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Figure 3-13. Fast Mode External Data Memory Read Cycle (WS = 00B) Figure 3-14. Compatibility Mode External Data Memory Write Cycle (WS0 = 0) Figure 3-15. Compatibility Mode External Data Memory Read Cycle (WS0 = 0) 3709D–MICRO–12/ CLK ...

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Figure 3-16. MOVX with One Wait State (WS = 01B) CLK ALE Figure 3-17. MOVX with Two Wait States (WS = 10B) CLK ALE Figure 3-18. MOVX with Three Wait ...

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... IAP Note: 3709D–MICRO–12/11 Section 3.3.2.1 “Write Protocol” on page Table 3-4 and Table 3-5. IAP Access Settings for AT89LP52 SIGEN DMEN MOVX @DPTR 0 0 XDATA (0000–FFFFH) FDATA (0000–00FFH XDATA (0100–FFFFH XDATA (0000–FFFFH) FDATA (0000–00FFH) ...

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Special Function Registers A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 4-1. Note that not all of the addresses are occupied, and unoccupied addresses may not be imple- mented ...

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Enhanced CPU The AT89LP51/52 uses an enhanced 8051 CPU that runs times the speed of standard 8051 devices ( times the speed of X2 8051 devices). The increase in performance is due ...

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Compatibility Mode Compatibility (12-Clock) mode is enabled by default from the factory or by setting the Compati- bility User Fuse. In Compatibility mode instruction bytes are fetched every three system clock cycles and the CPU operates with 6-state machine ...

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Bit 2 of AUXR1 is hard-wired as a logic 0. The DPS bit may be toggled (to switch data pointers) simply by incrementing the AUXR1 register, without altering other bits in the register unintentionally. This is the preferred method ...

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Table 5-2. DPD1 Table 5-3. – Data Pointer Configuration Register AUXR1 AUXR1 = A2H Not Bit Addressable DPU1 DPU0 Bit 7 6 Symbol Function DPU1 Data Pointer 1 Update. When set, MOVX @DPTR and MOVC @DPTR ...

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System Clock The system clock is generated directly from one of three selectable clock sources. The three sources are the on-chip crystal oscillator, external clock source, and internal RC oscillator. A dia- gram of the clock subsystem is shown ...

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An optional 5 MΩ on-chip resistor can be connected between XTAL1 and GND. This resistor can improve the startup characteristics of the oscillator especially at higher frequencies. The resistor can be enabled/disabled with the R1 User Fuse Figure 6-2. Note: ...

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System Clock Divider The CDV source by powers of 2. The clock divider provides users with a greater frequency range when using the Internal Oscillator. For example, to achieve a 230.4 kHz system frequency when using the RC oscillator, ...

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Reset During reset, all I/O Registers are set to their initial values, the port pins are set to their default mode, and the program starts execution from the Reset Vector, 0000H. The AT89LP51/52 has five sources of reset: power-on ...

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Table 7-1. SUT Fuse 1 7.2 Brown-out Reset The AT89LP51/52 has an on-chip Brown-out Detection (BOD) circuit for monitoring the V during operation by comparing fixed trigger level. The trigger level V nominally 2.0V. The purpose of ...

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The AT89LP51/52 includes an on-chip Power-On Reset and Brown-out Detector circuit that ensures that the device is reset from system power up. In most cases a RC startup circuit is not required on the RST pin, reducing system cost, and ...

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CPU when an interrupt is generated. The timer and UART peripherals continue to function dur- ing Idle. If these functions are not needed during idle, they should be explicitly disabled by clearing the appropriate control bits in their respective SFRs. ...

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Interrupt Recovery from Power-down Two external interrupt sources may be configured to terminate Power-down mode: external interrupts INT0 (P3.2) and INT1 (P3.3). To wake up by external interrupt INT0 or INT1, that inter- rupt must be enabled by setting ...

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Figure 8-3. PWD XTAL1 RST Internal Clock Internal Reset 8.3 Reducing Power Consumption Several possibilities need consideration when trying to reduce the power consumption in an 8051-based system. Generally, Idle or Power-down mode should be used as often as possible. ...

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The Timer 2 Interrupt is generated by a logic OR of bits TF2 and EXF2 in register T2CON. Neither of these flags is cleared by hardware when the CPU vectors to the service rou- tine. The service routine ...

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If the instruction in progress is RETI, the additional wait time cannot be more than 9 cycles (a maximum of 4 more cycles to complete the instruction in progress, plus a maximum of 5 cycles ...

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Table 9-2. IE – Interrupt Enable Register IE = A8H Bit Addressable EA – Bit 7 6 Symbol Function Global enable/disable. All interrupts are disabled when When each interrupt source is enabled/disabled by setting ...

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I/O Ports The AT89LP51/52 can be configured for between 32 and 36 I/O pins. The exact number of I/O pins available depends on the clock, external memory and package type as shown in 1. Table 10-1. Clock Source External ...

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Table 10-3. – Port Mode Register PMOD PMOD = C1H Not Bit Addressable P3M1 P3M0 Bit 7 6 Symbol Function P3M Port 3 Configuration Mode 1-0 P2M Port 2 Configuration Mode 1-0 P1M Port 1 Configuration Mode 1-0 P0M ...

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Figure 10-1. Quasi-bidirectional Output Figure 10-2. Input Only Figure 10-3. Input Circuit for P3.2, P3.3, P4.6 and P4.7 10.1.3 Open-drain Output The open-drain output configuration turns off all pull-ups and only drives the pull-down transistor of the port pin when ...

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Push-pull Output The push-pull output configuration has the same pull-down structure as both the open-drain and the quasi-bidirectional output modes, but provides a continuous strong pull-up when the port latch contains a logic “1”. The push-pull mode may be ...

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Port Alternate Functions Most general-purpose digital I/O pins of the AT89LP51/52 share functionality with the various I/Os needed for the peripheral units. Alternate functions are connected to the pins in a logic AND fashion. In order to enable the ...

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Timer 0 and Timer 1 The AT89LP51/52 has two 16-bit Timer/Counters, Timer 0 and Timer 1, with the following features: • Two independent 16-bit timer/counters with 8-bit reload registers • UART baud rate generation using Timer 1 • Output ...

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Mode 0 – 13-bit Timer/Counter Both Timers in Mode 0 are 8-bit Counters with a divide-by-32 prescaler. Mode 0 operation as it applies to Timer 1. As the count rolls over from all “1”s to all “0”s, it sets ...

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Mode 2 – 8-bit Auto-Reload Timer/Counter Mode 2 configures the Timer register as an 8-bit Counter (TL1) with automatic reload, as shown in Figure TH1, which is preset by software. The reload leaves TH1 unchanged. Mode 2 operation is ...

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Table 11-2. – Timer/Counter Control Register TCON TCON = 88H Bit Addressable TF1 TR1 Bit 7 6 Symbol Function Timer 1 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when the processor vectors TF1 to interrupt ...

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Figure 11-5. Timer 0/1 Toggle Mode 2 Waveform FFh THx Tx Table 11-4. TMOD – Timer/Counter Mode Control Register TMOD Address = 089H Not Bit Addressable GATE1 C/T1 Bit 7 6 Symbol Function Timer 1 Gating Control. When set, Timer/Counter ...

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Timer 2 The AT89LP51/52 includes a 16-bit Timer/Counter 2 with the following features: • 16-bit timer/counter with one 16-bit reload/capture register • One external reload/capture input • Up/Down counting mode with external direction control • UART baud rate generation ...

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Timer 2 Registers Control and status bits for Timer 2 are contained in registers T2CON (see T2MOD (see 16-bit timer register for Timer 2. The register pair {RCAP2H, RCAP2L} at addresses 0CBH and 0CAH are the 16-bit Capture/Reload register ...

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Capture Mode In the Capture mode, Timer fixed 16-bit timer or counter that counts up from MIN to MAX. An overflow from MAX to MIN sets bit TF2 in T2CON. If EXEN2 = 1, a 1-to-0 ...

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Figure 12-2. Timer 2 Diagram: Auto-Reload Mode (DCEN = 0) OSC ÷CDV ÷TPS Figure 12-3. Timer 2 Waveform: Auto-Reload Mode (DCEN = 0) MAX BOTTOM MIN 12.3 Down Counter Setting DCEN = 1 enables Timer 2 to count ...

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Figure 12-5. Timer 2 Diagram: Auto-Reload Mode (DCEN = 1) ÷TPS The timer overflow/underflow rate for up-down counting mode is the same as for up counting mode, provided that the count direction does not change. Changes to the count direction ...

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Figure 12-6. Timer 2 in Baud Rate Generator Mode OSC ÷CDV TRANSITION DETECT OR T2EX PI N 12.5 Frequency Generator (Programmable Clock Out) Timer 2 can generate a 50% duty cycle clock on T2 (P1.0), as shown ...

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External Interrupts The INT0 (P3.2) and INT1 (P3.3) pins of the AT89LP51/52 may be used as external interrupt sources. The external interrupts can be programmed to be level-activated or transition-activated by setting or clearing bit IT1 or IT0 in ...

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Special Function Register SCON, while the stop bit is ignored. The baud rate is programmable to either 1/16 or 1/32 the system frequency. • Mode 3: 11 bits are transmitted (through TXD) or received (through RXD): a start bit (0), ...

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Multiprocessor Communications Modes 2 and 3 have a special provision for multiprocessor communications. In these modes, 9 data bits are received, followed by a stop bit. The 9th bit goes into RB8. Then comes a stop bit. The port ...

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The Timer 1 overflow rate normally determines the baud rates in Modes 1 and 3. When Timer 1 is the baud rate generator, the baud rates are determined by the Timer 1 overflow rate and the value of SMOD1 according ...

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Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software. In this case, the baud rates in Modes ...

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Interrupt flag (RI) will be automatically set when the received byte contains either the “Given” address or the “Broadcast” address. The 9-bit mode requires that the 9th information bit be a “1” to indicate that the received information is an ...

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The Broadcast Address for each slave is created by taking the logic OR of SADDR and SADEN. Zeros in this result are trended as don’t cares. In most cases, interpreting the don’t cares as ones, the broadcast address will be ...

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The SMOD1 bit determines if the output data is stable for both edges of the clock, or just one. Table 14-5. SM2 Two-Wire configuration Mode 0 may ...

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Figure 14-3. Serial Port Mode 0 (Two-Wire) TIMER 1 O VERF sys 1 0 TB8 ÷2 ÷ SMOD1 WRITE SEND SHIFT RXD ( OUT ...

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... XCH A, R6 DJNZ R7, REVRS and shown in Figure . Three-Wire mode uses different I/Os from Two-Wire mode and Master MSB LSB MISO 8-Bit Shift Register MOSI AT89LP52 GPIO SCK Clock Generator Figure 14- possible to time share the Slave MSB MISO 8-Bit Shift Register MOSI ...

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Figure 14-5. Serial Port Mode 0 (Three-Wire) TIMER 1 O VERF sys 1 0 TB8 ÷2 ÷ SMOD1 WRITE SEND SHIFT MOSI (DATA OUT) SCK (SHIFT CLOCK) MISO ...

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More About Mode 1 Ten bits are transmitted (through TXD), or received (through RXD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in SCON. In ...

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Figure 14-6. Serial Port Mode 1 TIMER 1 TIMER 2 OVERFLOW OVERFLOW WRITE ÷2 TO SBUF “0” “1” SMOD1 “0” “1” TCLK “0” “1” INTERRUPT RCLK SAMPLE 1-TO-0 TRANSITION DETECTOR RXD TX CLOCK WRITE TO SBUF SEND DATA SHIFT D0 ...

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More About Modes 2 and 3 Eleven bits are transmitted (through TXD), or received (through RXD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On transmit, the 9th ...

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Figure 14-7. Serial Port Mode 2 CPU CLOCK SMOD1 1 SMOD1 0 3709D–MICRO–12/11 INTERNAL BUS INTERNAL BUS AT89LP51/52 71 ...

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Figure 14-8. Serial Port Mode 3 TIMER 1 TIMER 2 OVERFLOW OVERFLOW WRITE TO ÷2 SBUF “0” “1” SMOD1 “0” “1” TCLK “0” “1” INTERRUPT RCLK SAMPLE 1-TO-0 TRANSITION DETECTOR RXD TX CLOCK WRITE TO SBUF SEND DATA SHIFT D0 ...

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Programmable Watchdog Timer The programmable Watchdog Timer (WDT) protects the system from incorrect execution by trig- gering a system reset when it times out after the software has failed to feed the timer prior to the timer overflow. By ...

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Table 15-2. WDTCON – Watchdog Control Register WDTCON Address = A7H Not Bit Addressable PS2 PS1 Bit 7 6 Symbol Function PS2 Prescaler bits for the watchdog timer (WDT). When all three bits are cleared to 0, the watchdog timer ...

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Instruction Set Summary The AT89LP51/52 is fully binary compatible with the 8051 instruction set. In Compatibility mode the AT89LP51/52 has identical execution time with AT89S51/52 and other standard 8051s. The difference between the AT89LP51/52 in Fast mode and the ...

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Table 16-1. DEC @Ri DEC A INC DPTR INC /DPTR MUL AB DIV Logical CLR A CPL A ANL A, Rn ANL A, direct ANL A, @Ri ANL A, #data ANL direct, A ANL direct, #data ORL ...

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Table 16-1. MOV A, #data MOV Rn, A MOV Rn, direct MOV Rn, #data MOV direct, A MOV direct, Rn MOV direct, direct MOV direct, @Ri MOV direct, #data MOV @Ri, A MOV @Ri, direct MOV @Ri, #data MOV DPTR, ...

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Table 16-1. ORL C, bit ORL C, /bit MOV C, bit MOV bit, C Branching JC rel JNC rel JB bit, rel JNB bit, rel JBC bit, rel JZ rel JNZ rel SJMP rel ACALL addr11 LCALL addr16 RET RETI ...

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Programming the Flash Memory The Atmel AT89LP51/52 microcontroller features 8K bytes of on-chip In-System Programmable Flash program memory and 256bytes of nonvolatile Flash data memory. In-System Program- ming allows programming and reprogramming of the microcontroller positioned inside the end ...

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The Parallel interface is a special mode of the serial interface, i.e. the serial interface is used to enable the parallel interface. After enabling the interface serially over P1.7/SCK and P1.5/MOSI, P1.5 is reconfigured as an active-low output enable (OE) ...

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... Fuse Write with Auto-Erase command using the temporary data. Lock bits are treated in a simi- lar manner to fuses except they may only be erased (unlocked) by Chip Erase. Table 17-1. Memory CODE User Signature Atmel Signature Figure 17-3. AT89LP52 Memory Organization 3709D–MICRO–12/11 Table 17-1 and Figure AT89LP51/52 Memory Organization Capacity ...

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Command Format Programming commands consist of an opcode byte, two address bytes, and one or 64 data bytes. Figure 17-4 on page 82 A sample command packet is shown in select. Command bytes are issued serially on MOSI. Data ...

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Figure 17-5. ISP Command Packet (Serial Byte) SCK MOSI Opcode MISO X Figure 17-6. ISP Command Packet (Serial Page) SCK MOSI Opcode MISO X ...

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Table 17-2. Programming Command Summary Command (1) Program Enable (3) Parallel Enable Chip Erase Read Status Write Code Byte Read Code Byte Write Code Page Write Code Page with Auto-Erase Read Code Page Write Data Byte Read Data Byte Write ...

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... Atmel Signature Bytes: Address: 0000H AT89LP51: 1EH AT89LP52: 1EH 8. Symbol Key: a: Page Address Bit s: Half Page Select Bit b: Byte Address Bit x: Don’t Care Bit 17.4 Status Register The current state of the memory may be accessed by reading the status register. The status reg- ister is shown in Table 17-3 ...

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User Signature Array, Atmel Signature Array, and User Configuration Fuses are still allowed. The Lock Bits will not disable FDATA or IAP programming ...

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Table 17-5. User Configuration Fuse Definitions Address Fuse Name 07H Tristate Ports 08H In-Application Programming 09H R1 Enable Notes: 1. The default state for Tristate Ports is 00h. All other fuses default to FFh. 2. Changes to these fuses will ...

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Figure 17-9. Serial Programming Power-up Sequence MISO MOSI 17.9.2 Power-down Sequence Execute this sequence to power-down the device after programming. 1. Drive SCK low. 2. Wait at least t 3. Wait at least t 4. Wait at least t 5. ...

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Figure 17-11. In-System Programming (ISP) Start Sequence 17.9.4 ISP Exit Sequence Execute this sequence to exit ISP mode and resume CPU execution mode. 1. Drive SCK low. 1. Wait at least t 2. Tristate MOSI. 3. Wait at least t ...

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Figure 17-13. ISP Byte Sequence Figure 17-14. Serial Programming Interface Timing RST SCK MISO MOSI Figure 17-15. Parallel Programming Interface Timing RST SCK OE P0 AT89LP51/52 90 SCK MOSI MISO Data Sampled t t ...

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Timing Parameters The timing parameters for and Figure 17-15 Table 17-6. Symbol t CLCL t PWRUP t t PWRDN SHSL t SLSH ...

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Electrical Characteristics 18.1 Absolute Maximum Ratings* Operating Temperature ................................... -40°C to +85°C Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin with Respect to Ground......-0.7V to +5.5V Maximum Operating Voltage ............................................ 5.5V Total DC Output Current ........................................... 150.0 ...

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Minimum V for Power-down is 2V Inputs are TTL-compatible when V 18.3 Typical Characteristics The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins ...

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Figure 18-2. Idle Supply Current vs. Vcc (1.8432 MHz Internal Oscillator) AT89LP51/52 94 Idle Supply Current vs. Vcc 1.8432 MHz Internal Oscillator 0.60 Compatibility Mode 0.45 0.30 0.15 0.00 2.0 2.5 3.0 3.5 Vcc (V) 0.8 Fast Mode 0.6 0.4 ...

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Supply Current (External Clock) Figure 18-3. Active Supply Current vs. Frequency 3709D–MICRO–12/11 Active Supply Current vs. Frequency External Clock Source 8 Compatibility Mode Frequency (MHz) 20 Fast Mode ...

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Figure 18-4. Idle Supply Current vs. Frequency AT89LP51/52 96 Idle Supply Current vs. Frequency External Clock Source 3.0 Compatibility Mode 2.5 2.0 1.5 1.0 0.5 0 Frequency (MHz) 6 Fast Mode ...

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Quasi-Bidirectional Input Figure 18-5. Quasi-bidirectional Input Transition Current at 5V Figure 18-6. Quasi-bidirectional Input Transition Current at 3V 3709D–MICRO–12/11 0.0 0.5 1.0 1.5 2.0 2.5 0 -30 -60 -90 -120 -150 V IL 0.0 0.5 1.0 1.5 0 -10 ...

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Quasi-Bidirectional Output Figure 18-7. Quasi-Bidirectional Output I-V Source Characteristic at 5V Figure 18-8. Quasi-Bidirectional Output I-V Source Characteristic at 3V AT89LP51/ -20 -40 -60 -80 -100 -120 -140 V OH 1.0 1.5 2.0 0 ...

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Push-Pull Output Figure 18-9. Push-Pull Output I-V Source Characteristic at 5V Figure 18-10. Push-Pull Output I-V Source Characteristic at 3V 3709D–MICRO–12/ -10 V OH1 ...

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Figure 18-11. Push-Pull Output I-V Sink Characteristic at 5V Figure 18-12. Push-Pull Output I-V Sink Characteristic at 3V Note: 18.4 Clock Characteristics The values shown in this table are valid for T Figure 18-13. External Clock Drive Waveform AT89LP51/52 100 ...

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Table 18-1. External Clock Parameters Symbol Parameter (1) 1/t Oscillator Frequency CLCL t Clock Period CLCL t External Clock High Time CHCX t External Clock Low Time CLCX t External Clock Rise Time CLCH t External Clock Fall Time CHCL ...

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External Memory Characteristics The values shown in this table are valid for T ating conditions, load capacitance for Port 0, ALE and PSEN = 100 pF; load capacitance for all other outputs = 80 pF. Parameters refer to Figure ...

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Figure 18-14. External Program Memory Read Cycle ALE PSEN PORT 0 PORT 2 Figure 18-15. External Data Memory Read Cycle ALE RD t AVLL PORT 0 PORT 2 P2 Figure 18-16. External Data Memory Write Cycle ALE WR t AVLL ...

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Serial Port Timing: Shift Register Mode The values in this table are valid for V Symbol Parameter t Serial Port Clock Cycle Time XLXL t Output Data Setup to Clock Rising Edge QVXH t Output Data Hold after Clock ...

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Float Waveform Note: 1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when 100 mV change from the loaded V 18.8.3 ...

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I Test Condition, Power-down Mode, All Other Pins are Disconnected AT89LP51/52 106 RST DD GND POL (NC) XTAL2 XTAL1 GND = 2V to 5.5V DD 3709D–MICRO–12/11 ...

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... Body, Plastic Very Thin Quad Flat No Lead Package (VQFN/MLF) 3709D–MICRO–12/11 Ordering Code AT89LP51-20AU AT89LP51-20PU 4KB AT89LP51-20JU AT89LP51-20MU AT89LP52-20AU AT89LP52-20PU 8KB AT89LP52-20JU AT89LP52-20MU Package Types AT89LP51/52 Package Operation Range 44A 40P6 Industrial 44J (-40° 85° C) 44M1 44A ...

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Packaging Information 20.1 44A – TQFP e TOP VIEW C 0°~7° L SIDE VIEW Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. protrusion is 0.25 mm ...

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PDIP 40 1 BASE PLANE SEATING PLANE A1 .015 GAGE PLANE eC Lead Detail Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion. ...

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PLCC 1.14(0.045) X 45˚ 0.51(0.020)MAX 45˚ MAX (3X) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AC. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per ...

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VQFN/MLF D Marked Pin TOP VIEW BOTTOM VIEW Note: JEDEC Standard MO-220, Fig. 1 (SAW Singulation) VKKD-3. Package Drawing Contact: packagedrawings@atmel.com 3709D–MICRO–12/11 E Pin #1 Corner Pin #1 Option ...

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Revision History Revision No. Revision A – September 2010 Revision B – December 2010 Revision C – May 2011 Revision D – December 2011 AT89LP51/52 112 History • Initial Release • Added AT89LP51 device • Updated Device IDs • ...

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Table of Contents Features ..................................................................................................... 1 1 Pin Configurations ................................................................................... 2 .................................................................................................................... 3 2 Overview ................................................................................................... 6 3 Memory Organization ............................................................................ 11 4 Special Function Registers ................................................................... 24 5 Enhanced CPU ....................................................................................... 25 6 System Clock ......................................................................................... 29 7 Reset ...

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Table of Contents (Continued) 8 Power Saving Modes ............................................................................. 34 9 Interrupts ................................................................................................ 37 10 I/O Ports .................................................................................................. 41 11 Timer 0 and Timer 1 ............................................................................... 46 12 Timer 2 .................................................................................................... 51 13 External Interrupts ................................................................................. 57 14 Serial Interface ...

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Table of Contents (Continued) 15 Programmable Watchdog Timer ........................................................... 73 16 Instruction Set Summary ...................................................................... 75 17 Programming the Flash Memory .......................................................... 79 18 Electrical Characteristics ...................................................................... 92 19 Ordering Information ........................................................................... 107 20 Packaging Information ........................................................................ 108 21 Revision ...

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AT89LP51/52 iv 3709D–MICRO–12/11 ...

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